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AR# 23317

8.1i XST - With same primitive instantiated in a mixed language flow "_1" is added in the netlist primitive name that causes the design to error out in NgdBuild


In a mixed Verilog and VHDL design, when a primitive (for example, RAMB16_S9_S9) is instantiated in VHDL code and also in Verilog code, the generated NGC netlist adds "_1" ( RAMB_S9_S9_1) to the primitive name for the Verilog (or VHDL) instance. This is done to make the two instances unique.

At this point Translate fails with the following error report:

"ERROR:NgdBuild:604 - %s block '%s' with type '%s' is unexpanded"

It complains about not finding the netlist of the primitive.


This is an issue with XST 8.1i

You can work around this issue by following the steps below:

1. Instantiate a RAMB16_S9_S9 module in a single file.

2. Create a wrapper file for it.

3. Synthesize this file and get the Ngc/Edif file for this primitive (you get a new component).

4. Instantiate this primitive in one language. While in the files of the other language, you can use the primitive name RAMB16_S9_S9.

You can also use Coregen to get the netlist file and wrapper file.

This issue is fixed in ISE8.2i.

AR# 23317
Date 12/15/2012
Status Active
Type General Article
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