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AR# 23324

Virtex-4 RocketIO - Calibration Block v1.2.1 - USER_TXLOCK and/or USER_RXLOCK signals are not asserted


When Calibration Block v1.2.1 is used, USER_TXLOCK and/or USER_RXLOCK are never asserted, even when the MGT TXLOCK / RXLOCK ports are asserted. As the FPGA slice utilization increases, this issue can occur more often.


Calibration Block v1.2.1 timer circuits can misbehave due to setup/hold timing violations if DCLK is not stable upon the release of GSR. For example, if the design uses the DCM to generate the DCLK clock, this issue might occur. An FPGA reconfiguration is required to recover from this lockup. 


Calibration Block v1.2.2 provides a fix for this issue. Calibration Block v1.2.2 is a direct replacement for v1.2.1. The port interface is identical. The module/entity name is different because the version number is part of the name (...v1_2_1 becomes ...v1_2_2). 


Calibration Block v1.2.2 can be downloaded from (Xilinx Answer 22477).

AR# 23324
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article