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AR# 23352

MIG 1.5 - Are there any restrictions on DDR/DDR2 SDRAM pin assignments?

Description

Are there any restrictions on DDR/DDR2 SDRAM pin assignments?

Note: Starting with MIG 1.6, all pin-out guidelines are included in the Memory Implementation Guidelines chapter of the MIG User Guide. Please refer to the User Guide for the most up-to-date information on MIG pin assignments.

http://www.xilinx.com/products/intellectual-property/MIG.htm

Solution

The following rules apply to pin assignments for DDR and DDR2 SDRAM:  

- The DQ and DM bits of a byte are to be placed in the same bank as the associated DQS. The DQ bits must be kept close together for better routing. 
- It is recommended that address and control signals are to be placed in the same bank or at least as closely as possible if adjacent banks are needed. This will help in meeting timing closure. 
- Each bank that contains DQ/DQS/DM signals needs a loop back signal. 

If a bank is pin-limited and you need to free up a few pins, consider the following actions: 

- The loop back signals can be eliminated in Virtex-4 MIG 1.5 designs because they are no longer required. Other device families require significant user modifications to the MIG design to eliminate the PCB loop back. 
- The CKE signals can be tied together for multiple devices. 
- For DIMMs, noncritical features need not be implemented, such as PAR_IN/PAR_OUT and the SPD interface (SA, SPD, SCL).

AR# 23352
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article
IP
  • MIG