We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23390

12.1 EDK - How can I make my SDRAM controller visible in the Linker Script Generation GUI?


I have generated my own SDRAM controller using PLB_IPIF. However, when I use the Generate Linker Script option in EDK, unlike memories such as PLB BRAM and OCM memory, my SDRAM does not appear in the pull-down selection. Therefore, I cannot allocate code sections to it.

What can I do to make my memory controller visible to the tool as a memory type?


Use the following attributes in the MPD file:

PARAMETER c_baseaddr = 0xffffffff, DT = std_logic_vector, BUS = SOPB, CACHEABLE = TRUE, ADDR_TYPE = MEMORY
PARAMETER c_highaddr = 0x00000000, DT = std_logic_vector, BUS = SOPB

Refer to the "Defining Memory Size" section in the MPD chapter of the Platform Specification Format Reference Manual.
AR# 23390
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article