| AR# |
23395 |
| Part |
Coregen |
| Last Modified |
2006-09-17 00:00:00.0 |
| Status |
Active |
| Keywords |
CORE, COREGen, simulation, data, sheet, core, model, behavioral, functional, datasheet, non, cycle, accurate, fifo, FIFO, generator, asynchronous, |
Description
Keywords: CORE, COREGen, simulation, data, sheet, core, model, behavioral, functional, datasheet, non, cycle, accurate, fifo, FIFO, generator, asynchronous,
Some of the IP cores delivered in CORE Generator do not have accurate simulation models. How can I find out if there is a known limitation in a simulation model of an IP core being used?
Solution
The User Guide for each core contains a section on Simulation Models. If the Simulation Model has a known limitation, it will be detailed in this section of the Core's User Guide.
Known limitations for IP cores in the 8.2i release are as follows.
- FIFO Generator - Does not attempt to accurately model synchronization cycles for the Asynchronous FIFO. A structural model is provided as a closer representation of hardware.
- Block Memory Generator - Does not model collisions accurately.
- Single Port Block Memory - Does not model collisions accurately.
- Dual Port Block Memory - Does not model collisions accurately.
- Async FIFO v5.0 and newer - Does not attempt to accurately model synchronization cycles.
- Async FIFO prior to v5.0 - Attempted to model write-to-read latency. However, the model is not precise as asynchronous interfaces are impossible to model precisely.
- Distributed Memory Generator - Out-of-range writes are not modeled as per gates.
When simulating above cores with behavioral model, a message similar to following might occur:
** NOTE: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.# Time: 0 ps Iteration: 0 Instance: /top_tb_vhd/uut/uo/u0
The message is to warn you of the non-cycle accurate model, and the alternative is to use structural model simulation.
