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AR# 23407

LogiCORE PCI Express - Using a 125 MHz PCI Express REFCLK for prototyping on existing Virtex-4 boards

Description

PCI Express LogiCORE v3.1 revision 3 targeting Virtex-4 FX ES4 and later devices requires the use of a 250 MHz system clock input. PCI Express LogiCORE v3.1 revision 2 and earlier versions targeting Virtex-4 FX devices supported the use of 125 MHz system clock input. How can existing boards targeting Virtex-4 FX devices and 125 MHz reference clock be used with the PCI Express LogiCORE v3.1 revision 3 cores?

Solution

To use a 125 MHz reference clock on existing Virtex-4 prototype boards, you must set the following MGT and DCM attributes:

RXPLLNDIVSEL = 40 # Attribute for all active GT11 Components

TXPLLNDIVSEL = 40 # Attribute for all active GT11 Components

CLKIN_DIVIDE_BY_2 = FALSE; # Attribute for DCM

For example, if you are using the UCF in the example design provided with the x4 PCI Express LogiCORE v3.1 revision 3 core generated from CORE Generator, you would add the following lines to the UCF file:

# Attributes for all active GT11 Components

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" RXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" TXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" RXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" TXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST3" RXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST3" TXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST4" RXPLLNDIVSEL = 40;

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST4" TXPLLNDIVSEL = 40;

# Attribute for DCM

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/dcm" CLKIN_DIVIDE_BY_2 = FALSE;

IMPORTANT NOTE: Xilinx recommends that the above solution be used only with existing functional boards using Virtex-4 FX devices that do not contain a 250 MHz source. Xilinx strongly recommends use of 250 MHz reference clock for all new PCI Express designs that will target Virtex-4 FX ES4 and later devices.

AR# 23407
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article