In PLB2OPB bridge version 1.01.a, a PLB Read transaction is aborted by the processor as the OPB is retrying the transaction. This results in the PLB side of the bridge returning read data and a read acknowledgement when there is not a corresponding address-acknowledged PLB transaction.
This problem occurs because in the dead-lock prevention circuitry, PLB read transactions are not address-acknowledged until the transaction has completed on the OPB (i.e., not been retried on the OPB). In this case, the transaction was retried on the OPB and the PLB aborted the transaction before the PLB2OPB bridge could issue the re-arbitrate.
NOTE: This issue only occurs in PPC405 systems that are executing code from OPB memory.
If the system does not contain any OPB masters, you can work around this issue by using PLB2OPB bridge version 1.00.b (plb2opb_bridge_v1_00_b). If you use this work-around, you must also use the previous version of PLB_V34. However, if there is a Master on the OPB bus (such as OPB PCI), it requires the latest plb2opb_bridge patch.
This issue has been fixed and will be released in the EDK 8.2i SP1 release, which is scheduled for July 2006. If needed, Xilinx can provide the core for verification.
If you require the latest plb2opb_bridge patch, contact Xilinx Technical Support to request the latest patch:
You can also open an online WebCase with Xilinx Customer Support at: