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AR# 23481

Virtex-4 RocketIO - TXENOOB work-around for ES4, ES4S, Production Step 0

Description

In ES4, ES4S, and Production Step 0 silicon, the peak-to-peak amplitude of the differential output pins (TXP/TXN) can be higher than 65 mV when TXENOOB is asserted.

Solution

Under some conditions, the differential output is not attenuated when TXENOOB is asserted. To work around this issue, dynamically change the TXDAT_TAP_DAC and TXDAT_PRDRV_DAC attributes via the DRP (Dynamic Reconfiguration Port) of the GT11.

During periods when TXENOOB is asserted High, the TXDAT_TAP_DAC DRP setting must be dynamically changed to 11111 and the TXDAT_PRDRV_DAC DRP setting must be dynamically changed to 100. All other pre- and post-cursor settings should be left as the defaults. If pre-emphasis is used (pre- and/or post-cursor settings changed from default), pre-emphasis must be temporarily disabled during periods where TXENOOB is asserted High.

During normal operation (TXENOOB low), TXDAT_PRDRV_DAC must be restored to the default value of 111 and TXDAT_TAP_DAC must be restored to the default value of 01010. If used, any pre-emphasis settings (pre- and/or post-cursor settings) should also be restored.

The TXDAT_PRDRV_DAC is a 3-bit value. This 3-bit register is split over two DRP address locations as follows:

TXDAT_PRDRV_DAC[2] =>

MGTA: 54h, bit [0]

MGTB: 56h, bit [0]

TXDAT_PRDRV_DAC[1:0] =>

MGTA: 4Ch, bits [15:14]

MGTB: 4Eh, bits [15:14]

The TXDAT_TAP_DAC is a 5-bit value. This 5-bit register is at DRP address locations as follows:

TXDAT_TAP_DAC =>

MGTA: 4Ch, bits [11:7]

MGTB: 4Eh, bits [11:7]

NOTE: All pre-, post-, and data-cursor attributes span three DRP address spaces per MGT:

MGTA: 4Ch, 54h, 5Ch

MGTB: 4Eh, 56h, 5Eh

Calibration Block TXENOOB v.1.4.2 implements the TXENOOB work-around described in Solution 1 of this Answer Record. VHDL and Verilog design files, as well as instantiation templates are included in "mgt_cb_txenoob_v1_4_2.zip".

After clicking the link below, you will be prompted to log in to your Xilinx.com account and accept a license agreement. After doing so, click the "Download Design File" link.

https://secure.xilinx.com/webreg/clickthrough.do?iLanguageID=1&ipoid=24332297&category=-1210766&filename=mgt_cb_txenoob_v1_4_2.zip&file=660

Calibration Block TXENOOB v.1.4.2 is based on Calibration Block v1.4.1. That is, Calibration Block TXENOOB v1.4.2 is equivalent to Calibration Block v.1.4.1 with the added support of the TXENOOB work-around.

There are four additional ports on Calibration Block TXENOOB v1.4.2:

- TXOOB_MODE

- TXOOB_MODE_READY

- USER_TXENOOB

- GT_TXENOOB

When user logic asserts TXOOB_MODE, the calibration block accesses the DRP port to put the MGT into OOB mode. Specifically, the calibration block sets TXDAT_TAP_DAC to 11111 and TXDAT_PRDRV_DAC to 100 to put the MGT into OOB mode. The calibration block also forces all pre-emphasis attributes (both pre- and post-cursors) to default values during this time. Once this is complete, TXOOB_MODE_READY is asserted High.

The TXOOB_MODE_READY pin is High during normal data operation mode and High during OOB mode. It is Low while the calibration block is performing DRP accesses to bring the MGT into or out of OOB mode.

Note that there is one DCLK cycle of latency between TXOOB_MODE and TXOOB_MODE_READY (see waveform below). When user logic deasserts TXOOB_MODE, TXOOB_MODE_READY goes Low while the calibration block restores the values of TXDAT_TAP_DAC, TXDAT_PRDRV_DAC, and all pre-emphasis settings. Once this is done, the TXOOB_MODE_READY goes back to High and the MGT is back in nominal data operation mode.

The USER_TXENOOB input is simply passed through the calibration block to the GT_TXENOOB output. The GT_TXENOOB output connects directly to the TXENOOB port of the MGT.

NOTE: During OOB signaling mode (TXOOB_MODE = 1), do not transmit normal data or expect good data on the RX side, even if USER_TXENOOB signal is de-asserted. This mode is to be used only for OOB signaling (beaconing or electrical idles), and not for normal data transmission. Once back in nominal TX data mode (TXOOB_MODE = 0 and TXOOB_MODE_READY = 1), normal data transmission can resume.

Design Tip

Some protocols (e.g., PCIe) require that the device is in an electrical idle state when coming out of reset. There is a certain amount of latency for the cal block to configure the MGT for OOB mode. If the reset of the cal block is tied to the system reset, it is impossible for the device to be in electrical idle when coming out of system reset. To work around this problem, a local reset should be used for the cal block. The reset sequence can be staggered in such a way so that the cal block has finished configuring the MGT for OOB mode before coming out of system reset. In this way, when system reset is deasserted the MGT will be properly attenuated in an electrical idle state.

TXENOOB Ports
TXENOOB Ports

TXENOOB Timing
TXENOOB Timing

AR# 23481
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article