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AR# 23489

LogiCORE Block Memory Generator v2.1 - Release Notes and Known Issues for the Block Memory Generator Core (8.2i_IP1)


This Release Note is for the Block Memory Generator Core v2.1 released in 8.2i IP Update 1, and contains the following information:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 23479).

The Xilinx Block Memory Generator v2.1 LogiCORE should be used in all new Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-II/E, Spartan-3E, and Spartan-3 designs wherever block memory is required. This core supersedes the Single Port Block Memory v6.2 and Dual Port Block Memory v6.3 cores, but is not a direct drop-in replacement.


New Features in v2.1

- Supports Virtex-5 18K and 36K block RAM primitives

- Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, and Dual-Port ROM

- Supports parameterizable A and B port aspect ratios

- Supports parameterizable Read and Write port aspect ratios in Virtex-4 and Virtex-5 devices

- Optimized algorithm for even lower block RAM resource utilization

- Supports individual write enables per byte in Virtex-4 and Virtex-5 devices with support for 8-bit and 9-bit byte sizes

- VHDL and Verilog behavioral models optimized for faster simulation

Bug Fixes in v2.1

- Timing Performance severely impacted by XST synthesis bug in mux structure

- GUI does not restrict data width ratios when byte-write feature is used

- XCO file loading error due to byte write enable

- Corrected resource utilization tables in data sheet to indicate LUT resources without route-thru

- Increased accuracy of Block Memory resource utilization estimation in GUI

- Loading COE causes Core Generator to crash

- Core Generator fails to generate large memories

Known Issues in v2.1

(Xilinx Answer 23686) - Virtex-4, in structural (UniSim) simulation DOUTA changes on the wrong clock

(Xilinx Answer 23688) - Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"

(Xilinx Answer 22699) - Behavioral models do not flag collisions for asymmetric read-write ports

(Xilinx Answer 23744) - Invalid address input can cause the core to generate Xs on the DOUT bus

Device Issues

Please be aware of Virtex-5 Errata posted on:


Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

AR# 23489
Date 12/15/2012
Status Active
Type General Article
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