UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23497

LogiCORE XAUI v6.2 Core - Release Notes and Known Issues for the XAUI Core

Description

This Answer Record contains the Release Notes for the LogiCORE XAUI v6.2 Core that was released in 8.2i IP Update #1 and includes the following:  

 

- New Features in v6.2 

- Bug Fixes in v6.2 

- Known Issues in v6.2  

 

For installation instructions and design tools requirements, see (Xilinx Answer 23479).

Solution

New Features in v6.2 

 

- Support added for ISE 8.2i 

- Update GT11 attributes for better optimization for MGT based on further characterization 

- The following v6.1 rev1 and v6.1 rev2 enhancements are included in this release: 

* Virtex-4 FX reference clock frequency changed to 312.5 MHz. For more information, see (Xilinx Answer 23362) 

* CR 227266 - TXSYNC usage updated 

* CR 231655 - Updated for Virtex-4 FX CES4 

* CR 232614 - Revised GT11 Reset Circuitry 

 

Bug Fixes in v6.2 

 

- CR 233495 - UCF IOSTANDARD constraints not picked up in implementation 

- The following bug fixes delivered in v6.1 rev1 and v6.1 rev2 have been included in this release: 

*CR 228817 - Incorrect setting on CHAN_BOND_LIMIT 

*CR 229468 - Incorrect setting on TXCLK0_FORCE_PMACLK 

*CR 230207 - DCMs changed to High Frequency Mode 

 

Known Issues in v6.2 

 

-The Virtex-4 GT11 attribute ALIGN_COMMA_WORD is incorrect. For more information on this issue and details on how to work around it, see (Xilinx Answer 23684)

 

- The XAUI example design wrapper files are only tested with XST. The XAUI Verilog example design wrapper files contains XST specific synthesis constraints that will not be read by Synplify and other third party synthesis tools. These constraints include Virtex-4 GT11 attributes that are required for correct operation. For information on how to work around this issue, see (Xilinx Answer 24280)

 

-For Virtex-4, the USRCLK_STABLE input on the GT11 init blocks is tied to '1'. This should be connected to the locked output of the DCM. This has been corrected in v7.0 and later of the XAUI core. 

 

- For Virtex-4 GT11 attributes RXVCODAC_INIT and VCODAC_INIT bits 9:8 must be set to 00 otherwise the GT11 PLLs may not consistently lock. To correct for this they can be changed from a value of 10'b1000011111 to 10'b0000101001. This has been corrected in v7.0 and later of the XAUI core. 

 

-For Virtex-4, there have been some cases of channel bonding not working the first time and required a subsequent rxreset for the GT11 to channel bond. For XAUI v7.0 a block was added to monitor and in sure channel bonding is successful.

AR# 23497
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article