UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23508

8.2i IP Update #1 CORE Generator - IP-DSP What's New and Known Issues List

Description

Keywords: ISE, LogiCORE, Binary Counter, Comparator, Distributed Arithmetic FIR Filter, FIR Compiler, MAC FIR, MACC FIR, Multiplier Generator, DVB S2 FEC Encoder, FFT, Floating-point, Divider Generator, Pipelined Divider, Ram Based Shift Register, TCC Decoder 3GPP, CTC Encoder 802.16e, LDPC Encoder 802.16

This Answer Record for the #1 CORE Generator contains the IP-DSP "What's New" and "Known Issues" addressed in 8.2i IP Update 1 and contains the following:

- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 23479).
*URGENT - You must download the patch in (Xilinx Answer 24038) when installing ISE 8.2i Service Pack 3.

Solution

WHAT'S NEW in 8.2i IP UPDATE 1

LogiCORE Comparator v9.0
New Features in v9.0:
-- Support added for Virtex-5.
-- Support added for ISE 8.2i.
-- Area and speed improvements.

Bug Fixes in v9.0:
-- None.

LogiCORE Convolutional Encoder v6.0
New Features in v6.0:
-- Support for Virtex-5.
-- Removed Virtex and Spartan-II support from this version of the core. If targeting these architectures, please use v3.0.

Bug Fixes in v6.0:
-- CR227296 : Convolutional Encoder v5: Output rate is incorrect in template.

LogiCORE LDPC Encoder v1.0
New Features in v1.0
-- First release.
-- Low-latency encoder for IEEE 802.16e LDPC code.
-- Fully parameterized for all rates.
-- Fully scalable for all block sizes.

Bug Fixes in v1.0
-- None.

LogiCORE Multiplier Generator v9.0
New Features in v9.0:
-- Support for Virtex-5.
-- Improved resource usage for all multiplier variants.
-- User-configurable latency for all multiplier variants.
-- Enhanced range of hybrid multiplier implementations.
-- Option to use embedded multipliers to build a constant-coefficient multiplier.
-- Support for symmetric rounding in a single DSP48 or DSP48E.
-- Redesigned GUI with resource estimation.

Bug Fixes in v9.0:
-- CR223477 - Discrepancy between latency function and actual latency (obsolete).
-- CR223916 - Async reset does not work for Mult18x18-based multiplier handshaking signals (obsolete).
-- CR224108 - DSP48 35x18 mult - SCLR does not work on upper bits of product.
-- CR224179 - 35x35 DSP48 A-signed, B-unsigned output mismatch.
-- CR224180 - Dist mem CM fails with mismatch after synthesis (obsolete).
-- CR224195 - VHDL RFD output mismatch (obsolete).
-- CR224310 - VHDL output mismatch on CCMs.
-- CR225279 - Handshaking without CE does not work for hybrids (obsolete).
-- CR232171 - Remove references to A_SIGNED in the core.

LogiCORE RAM-based Shift Register
New Features in v9.0:
-- Support added for Virtex-5.
-- Support added for ISE 8.2i.
-- Area and speed improvements, especially for Virtex-5.

Bug Fixes in v9.0:
-- CR224975 - Address port width not correct.
-- CR215872 - Need for Verilog model.

LogiCORE Reed Solomon Encoder v6.0
New Features in v6.0
-- Support added for Virtex-5.
-- Support added for ISE 8.2i.
-- Now uses XST to elaborate the design.

Bug Fixes in v6.0
-- None.


KNOWN ISSUES IN 8.2i IP UPDATE 1

LogiCORE Comparator v9.0
-- No Known Issues.

LogiCORE Convolutional Encoder v6.0
-- No Known Issues.

LogiCORE LDPC Encoder v1.0
-- No Known Issues.

LogiCORE Multiplier Generator v9.0
-- Why does my Virtex-5 multiplier that is not fully pipelined give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware? See (Xilinx Answer 23697).
-- Why does my Virtex-5 Distributed RAM/ROM-based Constant Coefficient Multiplier (CCM) give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware? See (Xilinx Answer 23698).
-- Why does my non-Virtex-5 block RAM/ROM-based Constant Coefficient Multiplier (CCM) give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware? See (Xilinx Answer 23699).
-- Why does my Constant Coefficient Multiplier (CCM), with a constant of -1, fail to generate? See (Xilinx Answer 23700).
-- Why is the optimum latency incorrect for symmetric hybrid-based multipliers, when targeting Virtex-II, Spartan-3, or Spartan-3E? See (Xilinx Answer 23703).
-- Why is the output of my Constant Coefficient Multiplier (CCM) with a constant value of (2^64)-1 incorrect? See (Xilinx Answer 23704).
-- Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining? See (Xilinx Answer 23705).
-- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).
-- Why can I not add handshaking signals to my multiplier? See (Xilinx Answer 23598).
-- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).

LogiCORE RAM-based Shift Register v9.0
-- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).
-- Why is the LogiCORE RAM-based Shift Register v9.0 almost 10 times larger than the LogiCORE RAM-based Shift Register v8.0, when targeting Virtex or Spartan-II?
See (Xilinx Answer 23696).

LogiCORE Reed Solomon Encoder v6.0
-- No Known Issues.


KNOWN ISSUES in Existing IP

LogiCORE Add Sub v7.0
-- Why is my output result one less than the expected result? See (Xilinx Answer 23933).

LogiCORE CIC v3.0
-- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).
-- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).
-- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

LogiCORE Complex Multiplier v2.1
-- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

LogiCORE CORDIC v3.0
-- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).
-- LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require 4 extra clocks after asserting the ND signal, before the data will being processed? See (Xilinx Answer 23934).

LogiCORE Distributed Arithmetic FIR Filter (DA FIR) v9.0
-- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
-- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
-- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

LogiCORE DA FIR Filter, DDC, MAC FIR
-- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
-- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DCT v2.1
-- DCT can be implemented in Spartan-3 and Virtex-4 devices. See (Xilinx Answer 18937).

LogiCORE DCT v2.1
-- The DCT output width is incorrectly calculated, causing Java errors. See (Xilinx Answer 20459).

LogiCORE DDS v5.0
-- The DDS Data Sheet has an obsolete web link. See (Xilinx Answer 21397).

LogiCORE DDS v5.0
-- The DDS channel output does not operate as expected. See (Xilinx Answer 21474).

LogiCORE 1024-pt FFTv1.0
-- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0
-- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0
-- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0
-- No Verilog model is available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0
-- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

LogiCORE FFT
-- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings. See (Xilinx Answer 14861).
-- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1
-- Large FFT point size generation times. See (Xilinx Answer 21988).
-- Some bitwidth fail to allow core to implement. See (Xilinx Answer 20307).



LogiCORE FIR Compiler v1.0
-- How do I convert floating-point coefficients to fixed-point for Xilinx DA and MAC FIR filters? See (Xilinx Answer 5366).
-- How do I determine the latency of my filter? See (Xilinx Answer 22674).
-- Why does the FIR Compiler GUI crash when I enter an invalid Sample Frequency, or leave the Sample Frequency file empty? See (Xilinx Answer 22673).
-- Why does my single-rate or interpolating half-band fully parallel filter fail to generate for Virtex-4? See (Xilinx Answer 22705).
-- Why does my single rate MAC FIR filter fail to generate, giving me an empty or missing netlist and ERROR:sim - NgdBuild:153 or ERROR:NgdBuild:604? See (Xilinx Answer 22706).
-- Why do I get an Error:sim:57 when trying to generate a MAC FIR? See (Xilinx Answer 22675).
-- Why can I not use the multicolumn support when my coefficients are symmetrical? See (Xilinx Answer 22936).

LogiCORE Floating Point v2.0



LogiCORE MAC v4.0
-- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).

LogiCORE MAC FIR v5.1
-- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
-- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).
-- COE Errors reported in wrong format. See (Xilinx Answer 14202).
-- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).


LogiCORE Pipelined Divider v3.0
-- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v8.0
-- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).

LogiCORE Reed Solomon Decoder v5.1
-- Processing delay warning occurs for a 2-Channel Reed Solomon. See (Xilinx Answer 21769).

AR# 23508
Date Created 09/04/2007
Last Updated 03/30/2009
Status Archive
Type General Article