AR #23509 - LogiCORE VLYNQ - Release Notes and Known Issues

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LogiCORE VLYNQ - Release Notes and Known Issues

AR#	23509
Part	IP-DSP Horizontal
Last Modified	2008-03-19 00:00:00.0
Status	Active
Keywords	CORE Generator, IP, update, 8.2i, Ti, Texas Instruments, bus, serial, OPB

Description

Keywords: CORE Generator, IP, update, 8.2i, Ti, Texas Instruments, bus, serial, OPB

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE VLYNQ Bus Interface.

The following information is listed for each version of the core:
- New Features
- Bug Fixes
- Known Issues

You can access the VLYNQ Lounge at:
http://www.xilinx.com/products/ipcenter/DO-DI-VLYNQ.htm

Solution

General LogiCORE VLYNQ Issues
- Why does the OPB clock fail to restart after it has been stopped? See (Xilinx Answer 24047).

LogiCORE VLYNQ 1.3
Initial Release in ISE 10.1
New Features
- Support for device families Spartan-3ADSP and Virtex-5
Bug Fixes
- Core always times out irrespective of the type of license used - User's core times out even with a FULL license.
--- CR 450984/451159
- Core does not work when OPB_LENGTH is set to 1021, 1022 or 1023.
--- CR 454834
- Data sheet Inconsistencies
--- CR 437703, 437704, 430047, 450983
Known Issues
- N/A

LogiCORE VLYNQ 1.2
Initial Release in ISE 8.2i IP Update 2
New Features
- Support for Spartan-3A family devices.
Bug Fixes
- CR 234366: Updated UCF, example design and testbench files to resolve failing timing simulations.
- CR 423706: Bug fix for block memory reads.
Known Issues
- Why does the VLYNQ interface lock up after about four hours of operation? See (Xilinx Answer 29528).

LogiCORE VLYNQ 1.1
Initial Release in ISE 8.2i IP Update 1
New Features
- First release.
Bug Fixes
- N/A.
Known Issues
- Why does my VLYNQ Core fail to meet timing and my READ data not match my transmitted data? See (Xilinx Answer 23764).
- Why do I see corrupted data reads when using the VLYNQ core? See (Xilinx Answer 29527).