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AR# 23545

8.1i EDK/PAR - PAR failed after updating ml310_pci_design to 8.1i


Keywords: timing, ML310, treg, implementation

I am updating a ml310_pci_design to EDK 8.1i. After removing the ports PCI_ACK64_N and PCI_REQ64_N from the MHS file, I move along in the process until the following error message occurs during PAR:

"Starting initial Timing Analysis. REAL time: 25 secs
ERROR:Par:228 - At least one timing constraint is impossible to meet
because component delays alone exceed the
constraint. A physical timing constraint summary follows. This
summary will show a MINIMUM net delay for the paths.
The "Actual" delays listed in this summary are the UNROUTED delays
with a 100 ps timing budget for each route, NOT
the achieved timing. Any constraint in the summary showing a failure
("*" in the first column) has a constraint that
is too tight. These constraints must be relaxed before PAR can
Please use the Timing Analyzer (GUI) or TRCE (command line) with
the Mapped NCD and PCF files to identify the
problem paths. For more information about the Timing Analyzer,
consult the Xilinx Timing Analyzer Reference manual;
for more information on TRCE, consult the Xilinx Development System
Reference Guide "TRACE" chapter.

PAR done!
ERROR:Xflow - Program par returned error code 31. Aborting flow


Use the Timing Analyzer to view the timing report. The report indicates that the timing error is caused by the "ppc_trace" block. There is a SRL inferred in this block. The "treg", which is about 3.12 ns, makes it impossible to meet the period timing requirement of 3.3 ns.

To fix this issue, you can prevent the XST inferred SRL in "ppc_trace" block by using the "SHREG_EXTRACT" constraint in Verilog file (ppc_trace.v). For example, add one of the following to the code:

// synthesis attribute shreg_extract of c405trccycle_d7 is "no";


(* shreg_extract = "no" *)
reg c405trccycle_d7;
AR# 23545
Date 06/16/2006
Status Active
Type General Article
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