We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23572

10.1 EDK - How do I add a behavioral simulation model for black boxes in EDK?


I have designed a pcore that contains a CORE Generator FIFO. I have specified the FIFO netlist in the ".bbd" file. How can I specify the FIFO simulation model to EDK so that when I generate behavioral simulation files, EDK will automatically include the CORE Generator FIFO simulation model?


If you are using a CORE Generator netlist, you can add the generated VHDL wrapper file to the HDL directory of the custom IP. You also add this wrapper file name to the PAO file with an "lib" tag.

The wrapper file generated by CORE Generator is used to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. Make sure that you have compiled the XilinxCoreLib library.

If it is not a CORE Generator-generated netlist, you should provide a behavior simulation model yourself. This model will go in the simhdl directory instead of in the HDL directory. When modifying the PAO file, the "simlib" tag must be associated with your newly created simulation model.

The information for PAO files can be found at "Platform Specification Format Reference Manual" (psf_rm.pdf) -> "Peripheral Analyze Order (PAO)" in your EDK documentation directory.

AR# 23572
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked