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AR# 23597

LogiCORE Multiplier v8.0 - Why do I see simulation mismatches between the Verilog UniSim-based model and the back-annotated design?

Description

Why do I see simulation mismatches between the Verilog UniSim-based model and the back-annotated design?

Solution

This is a result of a bug in the UniSim-based model generation, which has been fixed in ISE 8.1i Service Pack 2.

AR# 23597
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article