LogiCORE Multiplier v8.0 - How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input?
Description
Keywords: CORE, CORE Generator, CORE Generator, coregen, signed, unsigned mult, generator, 8.0, 9.0
How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input?
Solution
This information has been added to the Multiplier v9.0 data sheet, scheduled to be released in July 2006.If this functionality is required, it can be implemented externally to the core with some simple RTL code, as shown:
VHDL example:
-- when a_sign is '0', a_data will be zero-extended and when a_sign is '1', a_data will be sign-extended
a_msb <= a_sign AND a_data(a'high);
a_core <= a_msb & a_data(a'high-1 downto a'low);