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AR# 23624

Virtex-4 DCM - DCM does not lock when DFS outputs are used and input clock is outside of DLL output range

Description

When using a Virtex-4 DCM, the LOCKED signal does not go High when the only clock outputs used are from CLKFX and CLKFX180, and the input clock frequency (CLKIN) is outside the supported operating frequency DLL outputs specified in the Virtex-4 Data Sheet (CLKIN_FREQ_DLL_(HF or LF)_(MS or MR)_MIN/MAX).

Solution

Virtex-4 LX and SX ES and step 0 must use the macro below to properly generate the DCM LOCKED signal when only DFS outputs are used and the CLKIN frequency falls outside the specified range for the DLL's CLKIN. Virtex-4 LX and SX step 1 and step 2 devices do not require this macro.

Virtex-4 FX ES, ES1, ES2, and ES3 must use the macro below to properly generate the DCM LOCKED signal when only DFS outputs are used and the CLKIN frequency falls outside the specified range for the DLL's CLKIN. Virtex-4 FX ES4, ES5 and 0 do not require this macro.

When using devices that do not require this macro, the proper production stepping level must be set in the UCF and you must turn off the DCM_AUTOCALIBRATE attribute; see (Xilinx Answer 21435) for how to turn this off. The DCM is safe from the effects of NBTI during this situation as the DFS does not suffer from the effects of NBTI.

Table 1 - Affected CLKIN Frequencies Based on DCM Attributes
Table 1 - Affected CLKIN Frequencies Based on DCM Attributes

The following macro provides the DFS LOCKED status when the clock input frequency falls outside the DLL clock input frequency range.

The module has two input ports: CLKIN and DFS_RESET. The DFS_RESET input is optional. The module outputs the CLKFX, CLKFX_180 and a DFS LOCKED signal. The DCM_ADV instantiation is used to provide the DFS functionality. Included in the module are three DCM attributes that must be set with the appropriate values for the application: CLKFX_DIVIDE, CLKFX_MULTIPLY, and DFS_FREQUENCY_MODE. Additional attributes can be added as needed.

Note: DI can be assigned to any value. If the synthesis tool requires DI assignment, assign DI to logic0. You can add additional attributes as needed.

// Verilog Example
// Macro/wrapper for DFS instance to read DFS_LOCKED status
//

`timescale 1ps/1ps
module dfs_wrap (CLKIN, DFS_RESET, CLKFX_OUT, CLKFX180_OUT, DFS_LOCKED);
input CLKIN, DFS_RESET;
output CLKFX_OUT, CLKFX180_OUT, DFS_LOCKED;

wire [15:0] DRP_OUT;
wire DRP_RDY;
reg [6:0] DRP_ADR;
reg DRP_EN;
reg DRP_WE;
reg RESET_FLOP;

assign logic0 = 1'h0;
assign logic1 = 1'h1;
assign DFS_LOCKED = DRP_OUT[0];

//initial begin
//DRP_ADR = 7'h3F;
//DRP_EN = logic0;
//RESET_FLOP = 0;
//end

DCM_ADV dfsinst (.CLK0(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(CLKFX_OUT),
.CLKFX180(CLKFX180_OUT),
.DO(DRP_OUT[15:0]),
.DRDY(DRP_RDY),
.LOCKED(),
.PSDONE(),
.CLKFB(),
.CLKIN(CLKIN),
.DADDR(DRP_ADR[6:0]),
.DCLK(CLKIN),
.DEN(DRP_EN),
.DI(),
.DWE(DRP_WE),
.PSCLK(),
.PSEN(),
.PSINCDEC(),
.RST(DFS_RESET)
);

//synthesis attribute CLKFX_DIVIDE of dfsinst 4;
//synthesis attribute CLKFX_MULTIPLY of dfsinst 2;
//synthesis attribute DFS_FREQUENCY_MODE of dfsinst "LOW";
//synthesis attribute CLK_FEEDBACK of dfsinst is "NONE";

always @(posedge CLKIN) begin
DRP_EN = logic0;
if (DFS_RESET)
RESET_FLOP = logic0;

else if (~RESET_FLOP && ~DFS_RESET)begin
DRP_EN = logic1;
DRP_WE = logic1;
DRP_ADR = 7'h3F;
RESET_FLOP = logic1;
end
else if (DRP_RDY) begin
DRP_EN = logic1;
DRP_WE = logic0;
DRP_ADR = 7'h30;
end
end
endmodule

-- VHDL Example
-- Macro/wrapper for DFS instance to read DFS_LOCKED status
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VComponents.all;

entity dfs_wrap is
port (
CLKIN : in std_logic;
DFS_RESET : in std_logic;
CLKFX_OUT : out std_logic;
CLKFX180_OUT : out std_logic;
DFS_LOCKED : out std_logic
);
end dfs_wrap;

architecture rtl of dfs_wrap is

signal DRP_OUT : std_logic_vector(15 downto 0);
signal DRP_RDY : std_logic;
signal DRP_ADR : std_logic_vector(6 downto 0);
signal DRP_EN : std_logic;
signal DRP_WE : std_logic;
signal RESET_FLOP : std_logic;

signal logic0 : std_logic;
signal logic1 : std_logic;
signal logic0_16b : std_logic_vector(15 downto 0);

begin

logic0 <= '0';
logic1 <= '1';
logic0_16b <= "0000000000000000";
DFS_LOCKED <= DRP_OUT(0);

dfsinst : DCM_ADV
generic map (
CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 100.0,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => FALSE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => CLKFX_OUT,
CLKFX180 => CLKFX180_OUT,
DO => DRP_OUT,
DRDY => DRP_RDY,
LOCKED => open,
PSDONE => open,
CLKFB => logic0,
CLKIN => CLKIN,
DADDR => DRP_ADR,
DCLK => CLKIN,
DEN => DRP_EN,
DI => logic0_16b,
DWE => DRP_WE,
PSCLK => logic0,
PSEN => logic0,
PSINCDEC => logic0,
RST => DFS_RESET
);

process (CLKIN)
begin
if (CLKIN'event and CLKIN = '1') then
if (DFS_RESET = '1') then
RESET_FLOP <= logic0;
DRP_EN <= logic0;
DRP_WE <= logic0;
DRP_ADR <= "0111111";
elsif (RESET_FLOP = '0' and DFS_RESET = '0') then
RESET_FLOP <= logic1;
DRP_EN <= logic1;
DRP_WE <= logic1;
DRP_ADR <= "0111111";
elsif (DRP_RDY = '1') then
RESET_FLOP <= RESET_FLOP;
DRP_EN <= logic1;
DRP_WE <= logic0;
DRP_ADR <= "0110000";
else
RESET_FLOP <= RESET_FLOP;
DRP_EN <= logic0;
DRP_WE <= DRP_WE;
DRP_ADR <= DRP_ADR;
end if;
end if;
end process;

end rtl;

AR# 23624
Date Created 09/04/2007
Last Updated 01/18/2013
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Less
IP
  • Digital Clock Manager (DCM) Module