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AR# 23625

9.1i Virtex-5 - Is there a summary list of ISE design tools known issues affecting Virtex-5 feature support?


Starting with ISE 8.2i, the Virtex-5 architecture is officially supported.

This Answer Record summarizes the 9.1i/8.2i ISE design tools known issues related to Virtex-5 features. If you are experiencing a problem that is not documented in this Answer Record, open a WebCase and submit a test case (if necessary, to reproduce the issue):


IMPORTANT: Detailed information about installing Virtex-5 LX220T and all SXT devices can be found in (Xilinx Answer 24544).

It should be noted that all other LX and LXT devices are supported in ISE 9.1i. Please install the latest service packs:



ISE 9.1.03i and ISE 9.1i Known Issues

Virtex-5 DCM - The DCM does not deskew the clock properly in the default mode of SYSTEM_SYNCHRONOUS (Xilinx Answer 25192)

Virtex-5 DCM - DCM does not function correctly if CLKFB is unused and grounded or tied high (Xilinx Answer 25200)

LogiCORE Endpoint Block v1.3 and Block Plus v1.6 for PCI Express - Simulations fail due to LLKRXDSTCONTREQN pin left unconnected (Xilinx Answer 24877)

9.1i Architecture Wizard - "ERROR:PhysDesignRules:1443 - Dangling pins on block:<instance_name/PLL_ADV_INST/instance_name/PLL_ADV_INST>" (Xilinx Answer 24724)

ISE 9.1.01i and ISE 9.1i Known Issues

9.1.01i Architecture Wizard - DCM to PLL mode does not allow DCM differential CLKIN input (Xilinx Answer 24725)

9.1i ChipScope - The IBERT cores are not properly detected in Virtex-5 SXT devices (Xilinx Answer 24736)

9.1i ChipScope -ILA/IBA cores do not trigger properly when using Virtex-5 SXT devices (Xilinx Answer 24735)

9.1i iMPACT - Support for SXT devices is not included until Service Pack 2 (Xilinx Answer 24514)

9.1i GTP SmartModel timing simulation - Incorrect data on TXN/TXP outputs in ModelSim VHDL/Verilog simulation (Xilinx Answer 24729)

Issues Fixed in ISE 9.1.02i (Service Pack 2)

9.1i XST - The Virtex-5 PCIE_EP block delays not available in XST, which leads to incorrect optimizations (Xilinx Answer 24726)

9.1 XST - XST misinterprets relative PERIOD constraint, which results in incorrect timing analysis (Xilinx Answer 24727)

Note to ISE 8.2i SP2 Users

8.2i ISE - With the release of ISE 8.2i SP2, Virtex-5 designs utilizing IODELAY, ISERDES, or the OSERDES components must be re-implemented. Designs that are not run through the implementation tools again will encounter failures in the implementation flow.

Current Known Issues

8.2i BitGen - Several Virtex-5 BitGen options, -g BRAM_Bist, -g GSR_sync, -g GTS_sync, do not work (Xilinx Answer 23808)

8.2i BitGen Virtex-5 - "ERROR:BitGen - Failed to program routethru" (Xilinx Answer 23913)

Issues Resolved in 8.2i ISE SP2

8.2i Virtex-5 - FIFO36_72 ALMOST_FULL / ALMOST_EMPTY parameters improperly defined as 9 bits wide (Xilinx Answer 23735)

8.2i Virtex-5 MAP - Over-utilized slice logic fails with placement errors rather than with over-mapped errors (Xilinx Answer 23801)

Issues Resolved in 8.2i ISE SP1

8.2i Virtex-5 PAR - "Xdm_Exception::DuplicateObjectFound object='/__binding[4]'" when running MPPR (Xilinx Answer 23638)

8.2i Virtex-5 PAR - BSCAN components are not placed correctly (Xilinx Answer 23639)

8.2i Virtex-5 PAR - Performance Evaluation Mode leads to unrouted design due to over constraining (Xilinx Answer 23640)

8.2i Virtex-5 MAP - DRC error due to MAP absorbing registers in DSP48E and leaving CEA1, CEB1 tied to GND (Xilinx Answer 23642)

8.2i Virtex-5 MAP - DRC error due to MAP absorbing registers in DSP48E and creating conflict between AREG and ACASCREG (Xilinx Answer 23643)

8.2i Virtex-5 MAP - RAM32M and RAMS64 are not being initialized correctly (Xilinx Answer 23644)

8.2i Virtex-5 DRC - "ERROR:PhysDesignRules:1492 - Incompatible programming for comp CFGLUT5_O6_OBU (Incorrect)" (Xilinx Answer 23645)

AR# 23625
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article