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8.1.03i UniSim, Simulation - DLL does not lock during Verilog simulation and does not generate any output clock

AR# 23647

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Topic SW-Sim Libraries
Last Updated 10/16/2008
Status Archive
Description

Keywords: UniSim, simulation, ModelSim, NC-Verilog DCM, lock, VCS, Verilog, DLL

DLL does not lock during Verilog simulation and does not generate any output clock. Why?

Solution

This problem has been fixed in the latest 8.2i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.2i Service Pack 1.
 
 
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