We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23654

Precision Synthesis - FAQ


This Answer Record includes general questions and answers about Precision Synthesis.


Precision Synthesis FAQ for Xilinx

Q. Why should I consider using Precision Synthesis?

- Precision Synthesis is a leading FPGA Synthesis tool for the simplest to the most complex FPGA designs and ASIC prototyping. It is the centerpiece of Mentor Graphics FPGA flow - the industry's most comprehensive solution for FPGA designers. Precision provides superior design analysis capabilities to efficiently produce high-quality designs. With its advanced optimization algorithms, Precision leverages all of the advanced features in modern FPGAs to produce the best quality of results.

Q. What is the Mentor Graphics FPGA Design Flow?

- Mentor Graphics offers the most comprehensive FPGA design flow from design creation, simulation, FPGA synthesis, hardware/software co-verification to board layout, providing designers a powerful suite of FPGA solutions. Precision Synthesis is the centerpiece of Mentor Graphics FPGA flow that includes such tools as HDL Designer Series, Catapult C Synthesis, ModelSim , Seamless FPGA, and IO Designer.

Q. What Timing Analysis capability does Precision Synthesis offer?

- Precision Synthesis offers an Award-Winning Timing Analysis capability to quickly find problems, locate their causes and implement solutions to accelerate time-to-market and effectively produce high-quality designs.

- Precision includes a fully interactive static timing analysis environment that allows users to modify constraints, reapply them to a synthesized database and perform an incremental timing analysis. Precision also offers a unique cross-probing capability between reports, schematics, and HDL source, improving designer productivity.

Q. What types of advanced optimization algorithms does Precision Synthesis offer to produce the best quality of results?

- Precision's powerful re-timing algorithm balances logic across register boundaries, hierarchy optimization minimizes logic between modules, DSP block and memory inference enables better resource mapping, implementation of FSM in dedicated synchronous RAM blocks to reduce logic consumption and pipelining inserts registers into multipliers. Precision Synthesis identifies when and where to employ these algorithms, easily improving area and performance.

Q. What industry standards does Precision Synthesis support?

- Precision provides superior language support for Verilog, VHDL and SystemVerilog 1800 for greater flexibility and reusability.

-Precision supports the industry standard Synopsys Design Constraints (SDC) format for constraints enabling reuse and increased ASIC prototyping productivity.

Q. How can I get my timing constraints into Precision Synthesis?

- You can use the industry-standard SDC format for designs that are both for ASIC and FPGA.

- In addition, Precision Synthesis supports UCF constructs for existing Xilinx designs.

- Constraints can be created via the graphical user interface (GUI) in Precision Synthesis and/or interactive command line window. You can also use global constraints (maximum clock frequency).

Q. Are all UCF keywords supported by Precision Synthesis? If not, which ones are supported?

- All of the common UCF commands are supported.

Q. What ASIC prototyping features does Precision Synthesis offer?

- Precision automatically synthesizes the DW01 and DW02 libraries, thereby accelerating, prototyping of DesignWare-intensive ASICs.

- To minimize the amount of FPGA clock skews, Precision has implemented an advanced gated clock conversion through hierarchy and for latches, shift registers, RAM, block multipliers and DSP blocks.

Q. Why do I need to use physical optimization in general?

- As process technologies incorporate smaller geometries, interconnect delay is becoming the dominant factor of the total delay. The Virtex-4 devices use 90 nm geometries, where interconnect delay can account for 80% of the total timing. For accurate timing analysis and meaningful timing optimization, physical synthesis becomes more critical.

- For the current generation of FPGA technologies and designs, RTL synthesis alone is often inadequate. Physical optimization complements RTL synthesis, making the latter much more efficient. Users gain more predictability of the flow when using RTL and physical optimization together. Precision Synthesis offers a complete, combined RTL and physical optimization solution.

- Equally important, Precision Synthesis is extremely useful when users need highly repeatable results in large, complex designs. This especially saves time and provides visibility when making small, incremental RTL changes after running an initial place and route.

Q. What types of design will benefit from the physical optimization techniques in Precision Synthesis?

- Almost any design will benefit from the highly productive flows enabled by Precision Synthesis, but certain designs will also benefit from physical optimization technology.

- Almost any design can benefit from integrated physical synthesis capabilities. The degree of benefit depends on the target technology of the FPGA, and the kind of design in question. A good rule of thumb is that when the ratio between the cell delay and the net delay in the critical path favors the net delay, then physical synthesis will likely be effective in improving performance.

- Physically aware synthesis has a proven track record of doing rather well in high density devices where the placement algorithms do not perform as well, where timing is critical, and where the traditional iterative RTL flow can be very time consuming.

- Typically, large complex designs on devices such as Virtex-II, Virtex-II Pro and Virtex-4 greatly benefit from using the physically aware features of Precision Synthesis.

Q. What kinds of algorithms are used to improve timing in physical optimization?

- Register Retiming: Physical retiming differs from logic retiming in two important ways. First, accurate interconnect delays allow accurate application of retiming. Second, the modified design elements can be optimally placed during retiming.

- Register Replication: Allowing placement to occur during register replication transforms this technique into a powerful timing optimization tool, rather than simply a way to limit fanout.

- Placement Optimization: Local placement changes driven by accurate critical path analysis allow Precision Synthesis to incrementally improve timing after place and route.

- Re-synthesis: Restructuring logic using back-annotated interconnect delays allows for accurate timing optimization that is difficult to do in logic synthesis.

Q. What is the Push Button Placement Reuse/ECO Feature?

- With Precision Physical the Placement Reuse/ECO feature preserves cell placements when the design functionality changes due to an Engineering Change Order (ECO).

- The Placement Reuse/ECO feature overlays placements at the gate level, such that only the logic affected by the changes is re-placed. This feature uses sophisticated placement and timing-driven "nudging" algorithms for optimal results. With this feature, completed sections of the design that have previously met timing goals remain untouched, thus assuring the shortest path to new functionality.

Q. Do I still need Xilinx Place and Route tools if I use Precision Synthesis?

- Yes, you do for both Precision RTL and Precision Physical. For Precision Physical, the tool starts physical optimizations after the design's initial Place and Route is done, which is how the tool initially obtains the necessary physical information. For Precision RTL, once a design has finished with compilation and synthesis, the tool generates an edif netlist for a down-stream Place and Route tool.

-Xilinx Place and Route tools are tightly integrated within Precision Synthesis. Users do not need to exit the Precision Synthesis design environment to run the Place and Route tool.

Q. What Xilinx devices are supported with Precision Synthesis?

- Precision RTL Supports:

XC9500 / XL / XV

Automotive Families

CoolRunner families

Spartan-II / -IIE / -3 / -3E / -3L

Virtex / -E / -II / -II Pro / -4

Qpro Virtex-E Millitary

Qpro Virtex-II Millitary

Qpro Virtex-II Rad Tolerant

Qpro Virtex High Rel

Qpro Virtex Rad Hard

- Precision Physical supports

Spartan-IIE / -3 / -3L

Virtex / -E / -II / -II Pro / -4

Qpro Virtex-E Millitary

Qpro Virtex-II Millitary

Qpro Virtex-II Rad Tolerant

AR# 23654
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article