Why is there a latency in the deassertion of the FULL, ALMOST_FULL, and PROG_FULL signals after the release of RST?
The FIFO Generator provides a single reset (RST) input that asynchronously resets all counters, output registers, and memories when asserted. When reset is implemented, it is synchronized internally to the core with each respective clock domain for setting the internal logic of the FIFO to a known state. This synchronization logic allows for proper timing of the reset logic within the core to avoid glitches and metastable behavior. Because of the synchronization logic used, there is a latency in the deassertion of the FULL, ALMOST_FULL, and PROG_FULL signals after the release of RST.