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AR# 23662

LogiCORE PCI Express and PCI Express PIPE - What causes error status bits to be set in the Device Control Register?


What causes the error reporting bits in the PCI Express Device Control Register to be set. This register is located at offset 0x08 in the PCI Express capability structure. In the Xilinx cores this register is located at address 0x60. This register is mapped to the user application through the core output cfg_dcommand[15:0].


The error reporting bits are set in response to specific conditions outlined by the PCI Express Base Specification. The following is a list of possible causes of this error. Each bit can be set for multiple reasons.

The Correctable Error Reporting bit or bit 0 is set for any of the following reasons:

Receiver Error (unrecognized symbol)

Replay Timeout

Replay Number Rollover (TLP has been retransmitted too many times)


Bad TLP (bad LCRC or Sequence Number)

User-indicated correctable error (cfg_err_cor_n signal)

The Non-Fatal Error Reporting bit or bit 1 is set for any of the following reasons:

Unsupported Request

User-indicated ECRC error (cfg_err_ecrc_n signal)

User-indicated Completion timeout (cfg_err_cpl_timeout_n)

User-indicated Completer Abort for Posted TLP (~cfg_err_cpl_abort_n & ~cfg_err_posted_n)

User-indicated UR for posted TLP (~cfg_err_ur_n & ~cfg_err_posted_n)

The Fatal Error Reporting bit or bit 2 is set for any of the following reasons:

Protocol error

Receive buffer overflow

Flow Control error

Malformed TLP

AR# 23662
Date 12/15/2012
Status Active
Type General Article
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