We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23680

LogiCORE SPI-4.2 (POS-PHY L4) v8.1 - Timing simulation is not supported for Virtex-5 designs


The SPI-4.2 v8.1 Core does not support back-anno timing simulation on the SPI-4.2 design targeting Virtex-5. The timing simulation file generated gives incorrect simulation results.


To work around this problem, re-run NGDBuild through back-anno with the following environment variable: 

XIL_MAP_NO_RAMB_UNTIE set to "0". 


This issue is fixed in ISE 8.2i Service Pack 2.

AR# 23680
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article