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AR# 23686

LogiCORE Block Memory Generator v2.1 - Virtex-4 RAMB16 VHDL UniSims - Incorrect collision behavior (DOA changes on CLKB)


While simulating the Block Memory Generator Core with asymmetric configuration, DOUTA of the RAMB16 primitives changes on rising edge of CLKB , which is incorrect. This might potentially cause a collision error.


This is UNISIM model issue addressed in 8.2i Service Pack 3.

To obtain status on this issue, please open a WebCase with Xilinx Technical Support:


AR# 23686
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article