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AR# 23689

LogiCORE Blk Men Gen v2.1 - Virtex-4, timing simulation fails due to setup time violation in X_SFF

Description

In Virtex-4, simulating Blk Mem Gen v2.1 Core might give the following timing violations: 

 

 # ** Warning: /X_SFF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; 

 # Expected := 0.131 ns; Observed := 0.096 ns; At : 15904.663 ns 

 # Time: 15904663 ps Iteration: 3 Instance: /top/bm_tb/test1_dut/bmg0/bmg0_bu2_u0_blk_mem_generator_valid_cstr_has_mux_a_a_dout_i_6 

 # Generator B: TIME: 16092 ns ID: 475 TX: _READ, addr: 5ca 

 # Generator A: TIME: 16124 ns ID: 474 TX: WRITE, addr: a0c, data: a0a4, we = 11 

 # ** ERROR: RTL A MONITOR [16124 ns]: DOUTA=X5, gold_doutA=65, tx_addr=433 

 

Due to the timing violation, the DOUT will output "x", resulting in incorrect output. 

 

The core has the following configuration: 

 

* True Dual Port 

* Write width a = 16, Read width a = 8, Write depth a = 1152, Read depth a = 2304 

* Write width b = 8, Read width b = 16, Write depth b = 2304, Read depth b = 1152 

* write mode a = write mode b = WRITE_FIRST 

* has_mem_output_regs = 1 (uses the embedded memory register), has_mux_output_regs = 1 (a register X_SFFs is built at the output of the mux) 

* has_ena = 1, has_enb = 1 

* has_regcea = 0, has_regceb = 1 

* has_ssra = 0, has_ssrb = 1 

* use_byte_wea = use_byte_web = 1, byte_size = 8

Solution

This issue is currently being investigated.  

 

To obtain status on this issue, please open a WebCase with Xilinx Technical Support: 

http://www.xilinx.com/support/techsup/tappinfo.htm

AR# 23689
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article