Keywords: CORE Generator, COREGen, IP, update, 8.1i, ip1_i, FIFO, generator, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft, simulation, behavioral, structural, UniSim, xilinxcorelib, v3.1, 8.2i
Behavioral simulation models are not supported for the built-in FIFO configuration.
You should generate a structural model when using a built-in implementation. If a behavioral model is generated, a FAILURE scenario will be generated within the model and the simulation will stop with a message to use structural models for built-in FIFO implementations.