My design fails with the following pack error when constrained by PlanAhead using LOC constraints. All of this logic packs into a slice successfully without constraints. Why does the pack fail when the logic is constrained?
"ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X51Y40) which
require the combination of the following symbols into a single SLICE
LUT symbol "receiver/synchroTOPInst/CFOCorri/cordInIM" (Output Signal =
MUXCY symbol "receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_cry_0"
(Output Signal = receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_cry_0/O)
MUXCY symbol "receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_cry_1"
(Output Signal = receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_cry_1/O)
XORCY symbol "receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_s_1" (Output
Signal = receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3)
The function generator receiver/synchroTOPInst/CFOCorri/cordInIM is unable
to be placed in the F position because the output signal doesn't match other
symbols' use of the F signal. The signal
receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_axb_0 already uses F. The
function generator receiver/synchroTOPInst/CFOCorri/cordInIM is unable to
be placed in the G position because the output signal doesn't match other
symbols' use of the G signal. The signal
receiver/synchroTOPInst/CFOCorri/CordicGPInst/I_3_axb_1 already uses G.
Please correct the design constraints accordingly."
The key logic involved looks like this:
where PlanAhead has applied the same LOC constraint on the LUT3 and MUXCY. The packer has a rule that inverters and buffers are not pushed backwards to LOC'd LUTs. This rule is used to control delay in certain applications. Since the LUT3 and LUT1 are not combined into a single LUT, the directed pack fails.
This pack rule can be relaxed in 8.1i by setting the following environment variable:
Linux and Solaris
setenv XIL_MAP_ALLOW_LOC_BACKWARD_PUSH 1
For general information about setting ISE environment variables, see (Xilinx Answer 11630).