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LogiCORE Multiplier v9.0 - Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining?

AR# 23705

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Topic IP-DSP Horizontal
Last Updated 04/06/2009
Status Active
Description

Keywords: CORE Generator, core, multiplier, mult, output, results, CORE Generator

Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining?

Solution

To work around this problem, add at least one stage of pipelining to your LUT-based multiplier, or use the embedded multiplier (DSP48E) in your Virtex-5 device.
 
 
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