8.2i EDK SP1 - "opb_pci_v1_02_a" bridge hangs with slow PCI clock during Configuration Read
Description
Keywords: opb_pci_v1_02_a, opb_pci, opb pci, Processor IP
When the PCI clock is slow relative to the OPB clock (300ns PCI, 10ns OPB), the bridge hangs on a configuration read of the Latency Timer during self configuration. Previous configuration reads of the status and command register complete.
Solution
This problem has been fixed in the latest EDK 8.2i Service Pack, available at:http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 8.2i Service Pack 1.