8.2i Virtex-5 - FIFO36_72 ALMOST_FULL / ALMOST_EMPTY parameters improperly defined as 9 bits wide

AR#	23735	Search For Another Answer
Topic	Unisim
Last Updated	07/19/2006
Status	Active

Description

Keywords: FIFO, Verilog, parameter, passing, UniSim

The parameters ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET are improperly defined as 9 bits. If using the UniSim model as a template for instantiations in XST, then XST might incorrectly interpret the parameter as binary.

Solution

To work around this issue, specify the parameter as 13 bits wide during instantiation:

FIFO36_72_EXP #(.ALMOST_EMPTY_OFFSET(13'h101)) u1 (ALMOSTEMPTY, ...