Keywords: FIFO, Verilog, parameter, passing, UniSim
The parameters ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET are improperly defined as 9 bits. If using the UniSim model as a template for instantiations in XST, then XST might incorrectly interpret the parameter as binary.
To work around this issue, specify the parameter as 13 bits wide during instantiation:
FIFO36_72_EXP #(.ALMOST_EMPTY_OFFSET(13'h101)) u1 (ALMOSTEMPTY, ...