We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23740

8.1 AccelDSP Synthesis Tool - Design exported to System Generator for DSP does not go through XST


If an AccelDSP Based Design with the Project Option "-register_inputs" set to TRUE is exported to System Generator, then connected into a larger design inside SystemGenerator, and that System Generator design is synthesized with XST, you will receive an error message stating that the ports "ac_InputReq" and "ac_OutputAvail" are unconnected. This error message is usually of the format:

WARNING: Xst:753 - "<pathname_to_AccelDSP_Exported_Design>" line <nnnn>:

Unconnnected output port 'ac_InputReq' of component '<name_of_AccelDSP_Design>'


ERROR:Xst:759 - "<pathname_to_AccelDSP_Exported_Design>" line <nnnn>: No default binding for component: <name_of_AccelDSP_Design>. Ports <ac_InputReq,ac_OutputAck> are not on the entity.


There is a negative interaction between the Project Option "-register_inputs" set to TRUE and the generated files for either Simulink or System Generator. The Project Option "-register_inputs" must be set to FALSE if exporting an AccelDSP Project to either System Generator or Simulink.

This is an issue only with the AccelDSP 8.1.01 release.

AR# 23740
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article