If an AccelDSP Based Design with the Project Option "-register_inputs" set to TRUE is exported to System Generator, then connected into a larger design inside SystemGenerator, and that System Generator design is synthesized with XST, you will receive an error message stating that the ports "ac_InputReq" and "ac_OutputAvail" are unconnected. This error message is usually of the format:
WARNING: Xst:753 - "<pathname_to_AccelDSP_Exported_Design>" line <nnnn>:
Unconnnected output port 'ac_InputReq' of component '<name_of_AccelDSP_Design>'
ERROR:Xst:759 - "<pathname_to_AccelDSP_Exported_Design>" line <nnnn>: No default binding for component: <name_of_AccelDSP_Design>. Ports <ac_InputReq,ac_OutputAck> are not on the entity.
There is a negative interaction between the Project Option "-register_inputs" set to TRUE and the generated files for either Simulink or System Generator. The Project Option "-register_inputs" must be set to FALSE if exporting an AccelDSP Project to either System Generator or Simulink.
This is an issue only with the AccelDSP 8.1.01 release.