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AR# 23744

LogiCORE Block Memory Generator - Invalid address on ADDR can cause the core to generate Xs on the DOUT bus during simulation

Description

If an invalid address is specified on the ADDR bus, Xs may appear on the DOUT bus during read operations, and during set and reset operations in the simulation. In the device, you might get unpredictable data on the DOUT.

Solution

The Xs on the output might continue to appear until the invalid address is overwritten internally with a new address. When output registers are used, this could take a couple of clock cycles. 

 

To avoid this issue, specify only the valid addresses. The valid address are 0 to the depth of the memory chosen during the core generation.

AR# 23744
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article