I have attempted to lock my DSP48 chain to start at a location in row zero, but PAR fails and the following message occurs:
ERROR:Place:609 - Placer was unable to create DSP48 cascade RPM for component fi/lk.1.ft/S_3[47:0].
The reason for this issue:
Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked. A problem was found where we should place MULT fi/lk.2.ft/S_3[47:0] off the edge of the chip in order to satisfy the relative placement requirement of this logic. The following components are part of this structure:
This message is only partially correct. The locked placement is invalid because of a conflict for shared C port connectivity, not because of an issue where a DSP48 would be placed "off the edge of the chip". In some cases, this is due to grounded unused C port connections conflicting with used C port connections in the same tile. MAP trims unused C port connections if the OPMODE is constant. If the OPMODE is not constant, the unused C port connections are not trimmed by default.
This problem has been fixed in ISE version 8.2i SP3. For earlier revisions, the problem can be avoided by setting the environment variable "XIL_MAP_DSP48_HS2" to cause MAP to unconditionally trim all grounded C ports on all DSP48s in your design. This solution is only feasible if all grounded C ports will never be used.
Linux and Solaris
setenv XIL_MAP_DSP48_HS2 1
For more general information about setting ISE environment variables, see (Xilinx Answer 11630).