When I try to create a timing group for my Virtex-5 design, the distributed RAM or SLICE RAMs are not listed. When is this going to be fixed?
This problem has been fixed in the latest ISE 8.2i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is ISE 8.2i Service Pack 2.