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AR# 23787

MIG v1.6 - Release Notes and Known Issues for MIG v1.6


This answer record contains the Release Notes for MIG v1.6, and includes the following:

  • Xilinx Software Support
  • Platform Support
  • Device Support
  • New Features and Changes
  • Known Issues
  • Installation Instructions
  • Getting Started
  • Additional Information


Xilinx Software Support

ISE Design Suite 8.1.03i is required for Virtex-4 and Spartan-3/-3E FPGA designs. ISE Design Suite 8.2.01i is required for Virtex-5 FPGA designs. No other ISE design tool versions have been tested with MIG 1.6.

Platform Support

MIG v1.6 is supported on Windows (32-bit) only.

Device Support

  • All Virtex-4 devices in all packages.
  • Virtex-5 FPGA is supported for the LX30, LX50, LX85, LX110, LX220, LX330 in the FF324, 676, 1153, and 1760 packages as defined by the product table.
  • All Spartan-3 devices in all packages are supported, except for the xc3s50 and xc3s200. There are not enough pins available on the xc3s50 and xc3s200 to create a 16-bit interface.

New Features and Changes

General New Features and Changes

  • Batch mode is now supported. Consult the user guide for more information.
  • UCF file is updated properly in "without DCM" cases.
  • Two output folders are now automatically generated; one with the test bench and one without the test bench. The checkbox to select or deselect a test bench is removed.
  • The "verify my ucf" option is now available to verify externally generated memory interface UCF files.

Virtex-5 and Virtex-4 New Features and Changes

  • Initial support for Virtex-5. DDR2 SDRAM and QDR II SRAM are supported with Verilog only. The memory components that were tested in hardware are currently supported. More memory types and features will be added in the next releases of MIG.
  • Virtex-5 and Virtex-4 designs allow the selection of DCI for data and address/control.
  • The Virtex-4 FIFO16 issue, as described in (Xilinx Answer 22462), is resolved for all designs.

Spartan-3 and Spartan-3E New Features and Changes

  • Spartan-3E FPGA Starter Kit board files are now available through the GUI.
  • Pin allocation efficiency improved after the switch to the +/-5 tile rule in MIG 1.5.
  • Added option for pin compatibility with prior MIG designs.
  • Mode register information is saved to "datasheet.txt" file.

Known Issues

  • For information on Virtex-5 DDR2 SDRAM and QDR II SRAM maximum frequencies, see (Xilinx Answer 23945).
  • For information on problems exiting initial startup calibration for certain configurations of Virtex-4 FPGA DDR2 SDRAM controllers, see (Xilinx Answer 24448).
  • For information on mapping the user interface address to account for the auto-precharge bit A10 for Virtex-4 FPGA DDR2 SDRAM controllers, see (Xilinx Answer 24432).
  • "Verify my ucf" does not work for "use Clock capable pins for strobes/read clocks." The tool currently does not verify whether clock-capable pins are used for strobes/rd clks.
  • You should be aware of the stepping level of your target devices and how this affects the maximum frequency achievable for the memory component that is generated. The MIG tool does not adjust the frequency for any particular stepping level in use. Please consult the relevant device data sheets or errata for more information on stepping. These documents are located at: http://www.xilinx.com/support/library.htm.
  • In the new timing analysis, it is possible to have negative results with some memory components; this is because some components have a higher Tac. The timing analysis sheet will show a negative result for some selected frequencies. If this occurs, you can change to a different memory component, or lower the frequency.
  • After installing MIG v1.6, the HELP -> About command in theCORE Generator tool does not indicate that the update is installed if the ZIP file method or method 1 below is used; this is expected behavior. To verify installation, a README file must be written to the root Xilinx directory indicating the version of the MIG tool installed. The file is either README_ise_82i_mig_v1_6.txt or README_ise_81i_mig_v1_6.txt, depending on the installation. For more information, see the "Installation Instructions" below.
    • See (Xilinx Answer 23898) regarding updates for the "README.txt" file in the Virtex-4 DDR2 SDRAM sim directory.
    • Spartan-3E Starter Kit DDR1 design files are available only in Verilog from MIG v1.6. The VHDL version of the files can be downloaded from:http://www.xilinx.com/txpatches/pub/applications/misc/s3e_starter_revd_mig_ddr[1].zip
  • Because of a problem in IP Update 1 FIFO Generator v3.1, VHDL simulations of RLDRAMII will cause the following failure:

    FAILURE: Use of behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is not currently supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information." SEVERITY FAILURE

    To fix this problem, download 8.2i IP Update 2. For more information in obtaining 8.2i IP Update 2, see (Xilinx Answer 23831).

Installation Instructions

Xilinx ISE Design Suite and CORE Generator Installation Requirements:

IMPORTANT NOTE: Memory controllers generated by MIG v1.6 targeting Virtex-4 and Spartan-3E devices have been fully regression tested using 8.1i SP3. For users who cannot use 8.1i SP3 when targeting Virtex-4 or Spartan-3/3E devices, see (Xilinx Answer 23943).

  • For Virtex-4 and Spartan-3/-3E, first ensure that you have installed ISE 8.1i with Service Pack 3 (8.1.03i).
  • For Virtex-5, first ensure that you have installed ISE 8.2 with Service Pack 1 (8.2.01i) along with IP Update 1.
  • Xilinx ISE design tools updates are available from the Download Center at:http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
  • For more information regarding ISE 8.2i IP Update 1, refer to (Xilinx Answer 23479).

MIG v1.6 Installation Instructions:

Method 1

1.Download MIG v1.6 from one of the following:

For Virtex-5 FPGA:

For Virtex-4, Spartan-3, or Spartan-3E FPGA:
(Enter your xilinx.com account name and password when prompted.)

2. Unzip this file into the root ISE 8.1i (Virtex-4 and Spartan-3/-3E) or ISE 8.2i (Virtex-5) installation (C:\Xilinx by default).

3. You might be prompted to allow it to overwrite existing files, select "Yes to All."

Method 2

This method works only if you are using the 8.1i CORE Generator tool. You can use either this method or download the ZIP file as described above. The automatic updates installer does not work for MIG if you are using 8.2i CORE Generator.

1. Launch the CORE Generator tool by selecting Start -> Xilinx ISE 8.1i -> Accessories -> CORE Generator from the Windows Start menu.

2. When the CORE Generator interface opens, select Tools -> Updates Installer.

3. The CORE Generator tool displays a dialog box with a warning indicating that it will exit after the installation is complete. Click Accept.

4. The CORE Generator tool connects you to www.xilinx.com and might ask for your xilinx.com User ID and password. If you are behind a firewall, you might have to enter the appropriate proxy settings.

5. The IP Updates Installer dialog box opens and displays a panel listing the available updates.

6. Select "ISE 8.1i MIG 1.6" and click the Install Selected button. The program might indicate that other installs are required. You can accept these informational messages. The CORE Generator tool downloads and installs the requested products and exits.

NOTE: Do not interrupt the installation process. During the process, you must accept various pop-up messages. If you have other windows open, the pop-ups might be hidden behind these windows. If you have any problems using this method, revert to Method 1 above.

Getting Started

To launch MIG, follow these steps:

1. Launch the CORE Generator tool by selecting Start -> Xilinx ISE 8.Xi -> Accessories -> CORE Generator.

2. Create a CORE Generator project.

3. Set your Xilinx part correctly; it cannot be changed inside MIG. Note that Virtex-4, Virtex-5, and Spartan-3/-3E devices are supported by MIG.

4. Note the location of the CORE Generator project directory. The "View by Function" tab to the left shows the available cores organized into folders.

5. Launch MIG by selecting Memories & Storage Elements -> MIG -> Memory Interface Generator.

6. In the Module Name text box, enter the name of the module to be generated. When you click Generate, the module files are generated in a directory with the same name as the module name in the CORE Generator project directory.

7. After generation, close the interface by selecting the Dismiss button.

The Generated IP tab to the left lists your generated modules. You can use the generated "ise_flow.bat" script or the ISE GUI to manually add the generated HDL files to a project. The MIG User Guide explains how the generated HDL files are used. You can access the MIG User Guide from the View Data Sheet links in the CORE Generator tool, or from the Data Sheet button in the MIG GUI.

Additional Information

You can access additional MIG and memory-related information at:
To access this URL, you must register specifically for the Memory Interface Generator product.

See Memory Interface Generator (MIG) under the "Resources" section.

You can search for other available IP cores at:

If you have comments, questions, or problems, contact Xilinx Technical Support at:

AR# 23787
Date 11/01/2012
Status Active
Type General Article
  • MIG
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