Virtex-5 - Speeds Files Revision History
Description
This Answer Record contains the Revision History for Virtex-5 family speeds files.
Solution
Speeds Files Revision History1.70 Release: Description and Explanation of Changes - 12.2
- For XQ5V devices, Updated IOB parameters
1.69 Release: Description and Explanation of Changes
- For XQ5V devices, Updated CLB, DSP, GTP, PLL, and RAMB parameters
1.68 Release: Description and Explanation of Changes - 12.1
- Updated GTP Hold values to match 1.66.
1.67 Release: Description and Explanation of Changes
- Updated some GTP_DUAL hold values for all three speed grades
- Updated values for -0, -3 for BUFR FMAX to 600ps
1.66 Release: Description and Explanation of Changes - 11.5
-Updated PLL_ADV for MINPERIOD parameters
1.65 Release: Description and Explanation of Changes - 11.2, 11,3 & 11,4
- Added XQ5V devices
- Updated timing paths for GT
1.64 Release: Description and Explanation of Changes - 11.1
- Updated values for IODELAY
1.62 Release: Description and Explanation of Changes - 10.1sp3
- Changed -1 and -2 speed grades for LX20T, FX30T, FX70T, & FX130T to PRODUCTION
- Changed all speed grades for FX100T to PRELIMINARY
- Changed -1 and -2 Speed grades for FX200T to PRELIMINARY
- Changed -3 speed grade for FX130T to PRELIMINARY
- Updates values for DCM, PLL, IODELAY, and BUFG components
1.61 Release: Description and Explanation of Changes - 10.1sp2
- Changed -1, -2, and -3 speed grades for LX155, LX155T to PRODUCTION
- Changed -1 and -2 speed grades for LX20T, FX30T, and FX70T to PRELIMINARY
- Updated values for BUFR/BUFIO/BUFG, IODELAY, Clock Networks, DCMs, GTPs, and PLLs
- Add Temperature and Voltage Prorating for PRODUCTION devices
1.60 Release: Description and Explanation of Changes - 10.1sp1
- Updated values for FX30T, FX70T for DCM, IODELAY and PLLs
- Updates to GTP
1.59 Release: Description and Explanation of Changes - 10.1
- Updated PPC delays
- Changed -3 speed grades for SX35T, SX50T to PRODUCTION
1.58 Release: Description and Explanation of Changes - 9.2.04
- Updates to PLL Source Synchronous compensation mode
- Updates to IDDR/ODDR (CE Paths and SAME_EDGE vs OPPOSITE_EDGE mode)
- Add ES1 stepping mode
1.57 Release: Description and Explanation of Changes - 9.2.03
- Updated PLL, PPC, GTP, and TEMAC delays
- Updated Pulse Width Limits on DCM components
1.56 Release: Description and Explanation of Changes
- Updates to GTP components
- Changed -1, -2, and -3 speed grades for LX50, LX50T, LX30, LX30T, LX85, LX85T, LX110, and LX110T to PRODUCTION
- Changed -1 and -2 speed grades for SX50T to PRODUCTION
1.55 Release: Description and Explanation of Changes
- Enhanced DCM Uncertainty Calculation by adding per output phase error factors
- Included tap variation (fabric delay) and jitter for IODELAY
- ODDR to Q path is analyzed only with rising edge clock
- Updated delays for PLL PMCD, DCM, and Phase Error
- Added -0 (Min) Speed Grade
1.54 Release: Description and Explanation of Changes
- Updated PLL, IOB, TEMAC, PPC, and DSP Delays
- Changed -1 and -2 speed grades for LX50, LX50T, LX110, and LX110 to PRELIMINARY
1.53 Release: Description and Explanation of Changes
- Updated block RAM delay records
- Updated routing delays around PPC
- Added support for Global Clock tile delays
- Updated DCM per tap delay based upon characterization data
- Updated DSP delay records and decreased several hold times
- Updated GTP delay values
- Increased buffer delay associated with PPC
- Fixed negative hold times on RST Pin of IDELAY
- Increased setup time for FF in ILOGIC
- Added Min Period checks for PLL_ADV component in SX and FX devices
- Updated PPC delay records
- Updated Min Period checks for PPC
1.52 Release: Description and Explanation of Changes
- Fixed Pulsewidth checks for DCM and PLL frequencies
- Updated Setup/Hold time with PPC
- Updated capacitance models on DCM and PLL
Updated delay types for PPC
- Updated delays for GTP
1.51 Release: Description and Explanation of Changes
- This version with 9.1.01i
- CLB
Adjusted 12 parameters in -3 speed grade, as well as two parameters in -2 speed grade and one parameter in -1 speed grade in F7MUX/Carry4/LAT_CE_Q
- Clocking
Reduced pin to pin (P2P) maxdelay for BUFG I->O
Reduced pin to pin (P2P) maxdelay for BUFR I->O for -1, -2, -3
Changed routing delays for global and regional clock buffers
Changed BUFR Fmax to 300 MHz for -3
Increased BUFR I->O for -1, -2, -3
Reduced I->O (bypass mode) for -1, -2, -3
- DCM
Corrected value for CLKIN_FREQ_FX_HF_MS_Min
Reduced D_DCM_OFFSET_BASE
Increased D_DCM_OFFSET_PERTAP
- I/O
D_IBUF_LVCMOS25 increased for -1 & -2
Relative min delays increased for some IBUF I/O Standards
- IODELAY
I/O delay values changed and now use a specific relative min value
- ILOGIC
CLK -> Q increased for all speed grades
D->CLK Setup decreased for -1, -2, -3
D->CLK Hold increased for -2, -3 and decreased for -1
- OLOGIC
(OFF) CLK -> Q (FF Mode) decreased for -1, -2, -3
(OFF) CLK -> Q (LAT Mode) increased for all speed grades
(TFF) CLK -> Q (FF Mode) increased for -2, -3
(TFF) CLK ->Q (LAT Mode) increased for all speed grades
- MONITOR
Added extra delay to -3 values for clock to out
- PCIe
Reduce Setup padding for -3,-2,-1
- PLL
Added D_PLL_OFFSET parameters for TRACE
- PPC
-- Changed the negative values for -2, -1 to be "slower" or the same with -3 in the cases where they were faster
-- Updated values based on STA
- RAMBFIFO
Various changes
1.51 Release: Description and Explanation of Changes
- Updated PPC, Clocking, DCM, IOB, and IODELAY
- Update derating factors for BUF and BUFIO
- This is the official version for 9.1i
1.50 Release: Description and Explanation of Changes
- Updated GTP, IODELAY, PLL, and IOB
- Added support for new devices
1.49 Release: Description and Explanation of Changes
- Updated delays for TEMAC, Clocking, DCM, DSP, IOB, and PCIe
- Updated Derating Factors
1.48 Release: Description and Explanation of Changes
- More accurate IODelay, IOI, PLL_Adv, PPC and SERDES/TEMAC
1.47 Release: Description and Explanation of Changes
- Updated the Clock Skew factors from 1.42; see (Xilinx Answer 23869)
1.45 Release: Description and Explanation of Changes
- Added new values for SERDES and IOI components
- Updated values for CLKB
- Updated CLOCKING, DSP, PPC, RCLK, DCM, PLL_ADV, IODELAY, and RAMFIFO36 components
- Updated hold times on input flip-flops with global clock and default delay
- Updated PLL and DCM pulse width checks
- Decreased setup time on CE1 to CLK paths for ISERDES components
- Increase in clock skew; see (Xilinx Answer 23869)
1.42 Release: Description and Explanation of Changes
- Updated CLB components
- Updated hold time values for IOI and SERDES components