Keywords: synthesis, translate, MAP, PAR, behavioral, timing, test bench, VHD, question mark
When I remove a VHDL file that has been added to my project as a "Simulation Only" source, the implementation processes (in the Synthesis/Implementation view) are changed to "Out of Date" (i.e. with the "?" icon) and all processes must be rerun. Removing a "Simulation Only" file should not affect the Synthesis/Implementation status.