We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23793

8.2i ISE - Removing "Simulation Only" file in Project Navigator changes the implementation status to "Out of Date"


Keywords: synthesis, translate, MAP, PAR, behavioral, timing, test bench, VHD, question mark

When I remove a VHDL file that has been added to my project as a "Simulation Only" source, the implementation processes (in the Synthesis/Implementation view) are changed to "Out of Date" (i.e. with the "?" icon) and all processes must be rerun. Removing a "Simulation Only" file should not affect the Synthesis/Implementation status.


This problem has been fixed in the latest ISE 8.2i Service Pack available at:
The first service pack containing the fix is ISE 8.2i Service Pack 2.
AR# 23793
Date Created 09/04/2007
Last Updated 04/16/2009
Status Archive
Type General Article