We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23810

ISE 14.7 MAP - ERROR:Pack:1568 - The DDR reg FOO failed join ILOGIC


My design failed during the packing stage of MAP with the following errors.


ERROR:Pack:1568 - The dual data rate register FOO failed to join an ILOGIC component as required. 

ERROR:Pack:1569 - The dual data rate register FOO failed to join an OLOGIC component as required.

What do these errors mean and how do I correct them?


These messages usually mean that the DDR Registers were not eligible to be packed into an ILOGIC/OLOGIC component. 

This is very similar to the issue of flip-flops failing to pack into I/O components.

However, DDR Registers do not have the alternative of packing into a Slice component, resulting in an error.  


Possible causes for the packing failure include: 

  • Invalid connectivity to I/O components. This may include unsupportable fanouts or inversions. 
  • Area Group Range constraints may prevent the pack. 
  • KEEP HIERARCHY constraints may prevent the pack. 
  • Incompatible shared control signals between the ILOGIC and OLOGIC component may prevent the pack. 


For this last case, the error may occur when a synthesis fanout limit has been applied to a reset line resulting in the reset line being partitioned into separate but logically equivalent nets, and the synthesizer fails to group the FF loads properly. 

n this case, the following work-arounds are available: 


  • Increase the synthesis fanout on the reset signal to prevent the partitioning of the signal. 


  • Manually group the reset lines and flip-flops in the design, ensuring that there is only one reset per ILOGIC/OLOGIC pair.
AR# 23810
Date Created 09/04/2007
Last Updated 01/08/2015
Status Active
Type General Article
  • FPGA Device Families
  • ISE