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AR# 23847

LogiCORE FIFO Generator v3.2 - Release Notes and Known Issues for 8.2i IP Update 2 (8.2i_Ip2)


Keywords: CORE, CORE Generator, COREGen, IP, update, 8.2i, ip2_im, FIFO, generator, fifogen, asynchronous, synchronous, common, clocks, memory,block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Note is for the FIFO Generator v3.2 Core released in 8.2i IP Update 2 and contains the following:

- New Features
- Bug Fixes
- Known Issues
- Documentation Update


New Features in v3.2
- Virtex-4 XA, Spartan-3E XA, Spartan-3 XA and Spartan-3A device support added
- Support for synchronous reset in common clock Block RAM and Distributed RAM implementations

Bug Fixes in v3.2
CR 423373: In v3.2, Synchronous reset feature is implemented for Common clock BRAM and DRAM. In order for the FIFO to start up at a valid state at power-up (to be able to write to the FIFO on the very first clock edge), the flags now power up at an "synchronous reset" state. Please refer to the User Guide for details about the new power-up and reset values.

CR 422741: VHDL Behavioral model simulation fails with following message:
Failure: FAILURE: Use of behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information. This failure was seen even for Distributed RAM and Block RAM type, and for Virtex-2.

CR 415411: VHDL Behavioral model simulation fails with a message, "Array lengths do not match", for the WR_DATA_COUNT flag for a First-Word-Fall-Through FIFO with Asymmetric Ports and "Use Extra Logic " option.

CR 419555: Verilog Behavioral model simulation of a First-Word-Fall-Through FIFO with Independent Clocks asserts the UNDERFLOW flags unexpectedly.

CR 235547: For Virtex-5 , Independent Clock, Built-in-FIFO, the programmable empty negate threshold was computed differently than the assert threshold.

CR 235545: Data count width defaults to an invalid value when the "Use extra logic" option for First-Word-Fall-Through is checked , then subsequently unchecked.

General Information
(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes User Guide in addition to data sheet. Where can I find the User Guide for the FIFO Generator?

Known Issues in v3.2
(Xilinx Answer 24002) For Block RAM and Distributed RAM FIFO, if the reset pin is not chosen, the reset type text in page 6 of the GUI Summary is displayed incorrectly as "Asynchronous" instead of "Not Selected".
(Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful and the warnings can be ignored.
(Xilinx Answer 24018) When running timing simulation for Virtex-5 design containing FIFO Generator built with Build-In-Fifo, the user might receive simulation error about TIEOFFREGCEAL connection problem
(Xilinx Answer 24019) Core cannot be generated for Independent Clock Block RAM FIFOs with input_depth=16 and output_depth=128 or input_depth=128 and output_depth=16
(Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
(Xilinx Answer 20278) PROG_EMPTY and PROG_FULL can produce false-assertions
(Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
(Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

Device Issues
Please be aware of Virtex-5 Errata posted on
FIFO Generator core with block Ram configuration is subject to all block RAM issues listed in the errata.

Documentation Changes
User Guide: Added a table describing the values for all output signals upon reset and power-up.

FIFO Generator v3.1 Known Issues
-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues
-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existiting FIFO Generator v3.1 issues, see (Xilinx Answer 22302).

AR# 23847
Date 09/21/2006
Status Active
Type General Article
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