| AR# | 23848 |
| Part | Coregen Dist Mem Generator |
| Last Modified | 2006-09-21 00:00:00.0 |
| Status | Active |
| Keywords | CORE Generator, COREGen, IP, update, 8.2i, ip2_im, mem, memory, asynch, asymmetric, non-symmetric, RAM, dist, gen |
Keywords: CORE Generator, COREGen, IP, update, 8.2i, ip2_im, mem, memory, asynch, asymmetric, non-symmetric, RAM, dist, gen
This Release Note is for the Distributed Memory Generator Core v3.2 released in 8.2i IP Update 2, and contains the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 23831).
The Xilinx Distributed Memory Generator v3.2 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE.
