AR# 23865: LogiCORE CAN - Incorrect value may be read by the Host in Loopback or Sleep Mode
AR# 23865
LogiCORE CAN - Incorrect value may be read by the Host in Loopback or Sleep Mode
Description
When attempting to read the status of Loop Back or Sleep Mode, it is possible for an incorrect value to be read from the OPB for one clock cycle.
Solution
When the Node is in Sleep Mode, reading the SLEEP bit in the Status Register may return an incorrect value. The impact of this issue is that reading the SLEEP bit in the Mode Select Register (Control Register) may not produce the correct indication whether the core is in SLEEP mode.
To work around this issue: 1) You can Poll the BBSY and BILDE bits in the Status Register. The node wakes up either when messages are written into the tx buffers or when there is traffic on the bus lines. To determine when the node has entered sleep mode, if BILDE bit is '1', the node has entered sleep mode provided its transmit buffers are empty (the host has to keep a count of the number of tx buffers that are empty- when writing a message increment the counter by 1, when TXOK ( status register bit) is '1' or TXOK interrupt bit is '1', decrement counter by 1). When BILDE is '1' and the number of empty tx buffers = the total number of configured buffers, node is in sleep mode. To determine the occurrence of wake up when the node is in sleep mode, once in sleep mode, writing messages to the tx buffer implies wakeup is imminent. If BBSY is '1', node has wakened up (self wake up by the node in sleep mode). In case the node is already in sleep mode, the node wakes up if BBSY is '1' (wake up of node in sleep mode due to external bus traffic). BBSY and BILDE are mutually exclusive, so polling only one of these bits is necessary.
It is also recommended that you disable the Interrupt Enable bits (EWKUP bit and ESLP bit in the IER), which should be programmed to a '0'.
When the Node is in Loop Back mode, reading the LBACK bit in the Status Register may return an incorrect value ( '0' instead of a '1' ). The impact of this error is low as the Loop Back mode can be entered only from the Configuration mode.
Work Around: The user can assume that after programming the LBACK bit in the Mode Select Register and the CEN bit in the (Software Reset Register), the node enters the loop back mode after a specified time "X". The delay "X" would be around 6 Can Clock Cycles.
It is also recommended that you disable the Interrupt Enable bits (EWKUP bit and ESLP bit in the IER) which should be programmed to a '0'.
The following issues apply only to Loopback and Sleep Modes which are features provided in Xilinx Logicore CAN in addition to the CAN Specification. Unless designers are using these features specifically in their current development, this issue can be safely ignored. This issue does not affect the CAN certification under C&S. This issue will be fixed in a future version and the CAN core will be recertified as part of Xilinx' normal release processes in 2007.