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AR# 23869

8.2i Speed File/Timing Virtex-5 - Larger clock skew in 8.2isp2 compared to 8.2isp1

Description

Keywords: service pack, derating, factor

When I run timing analysis for my Virtex-5 design in 8.2isp2, the clock skew from the BUFR components is very large. In 8.2isp1, the clock skew was reasonable. I also see large clock skew on my BUFIO components. When is this going to be fixed?

Solution

Clock skew is used during setup and hold analysis. The equation for clock skew is the clock path to the destination (Tclk2dest), minus the clock path to the source (Tclk2src), times a derating factor (Relative_Min_Factor), or clock skew = Tclk2dest - (Tclk2src * Relative_Min_Factor). The Relative Min Factor is used to give more accuracy to the clock skew calculations and OFFSET IN constraints.

In the speed file version 1.42 (8.2isp1) of Virtex-5, the Relative Min Factors for BUFR was 80% for -1 and -2, 90% for -3, and for BUFIO, it was 92% for all speed grades.

In the speed file version 1.45 (8.2isp2) for Virtex-5, the Relative Min Factors for BUFR are 12% for -3, 7% for -2, 10% for -1, and for BUFIO, it is 48% for -3, 45% for -2, and 42% for -1.

The Relative Min Factors are going to be changed back to the values in the 1.42 version, and is available in a tactical patch for 8.2isp2. The version with the corrected values is 1.47 for Virtex-5 in 8.2isp3.
AR# 23869
Date Created 09/04/2007
Last Updated 06/17/2008
Status Archive
Type General Article