I implemented an 8:1 mux to select from multiple global clocks. The mux was successfully implemented as a wide gate structure, but the router is failing with the following congestion warnings even though the design has very low utilization.
"WARNING:Route:438 - The router has detected an unroutable situation due to local congestion. The router will finish the rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too much logic into a single CLB. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such congested connections:
Congestion on : PINFEED(-94635,165792) signal : i_Pixel_Clk_0_ BUFGP
Congestion on : PINFEED(-94635,165792) signal : s_OutputChanne lSrcSel_8_0
This is an architecture limitation of Virtex-4. It is only possible for four unique global clocks to drive non-clock inputs in a single CLB. In this case, the CLB has eight unique clocks, so only four of them are routed and the four remaining clocks are not routed. A possible solution is to use four BUFGMUXs as 2:1 muxes and their outputs going to a 4:1 mux implemented in regular logic.