We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23878

Virtex-5 PLL - LOCKED does not go High when the REL pin is unused


Starting in 8.2i sp2, Architecture Wizard ties the REL port of the PLL_ADV primitive High, if it is unused. In this version (and previous versions), of the design tools, the REL pin must be tied High for the PLL to lock properly.

In 8.2i sp3 (and later versions of the design tools), the REL pin of the PLL_ADV must be left unconnected, or tied Low when REL is unused. Architecture Wizard still ties REL High, causing the PLL not to lock on the board.


This issue has been fixed in 9.1i sp3 of the Architecture Wizard. In 9.1i sp3 (and later design tools), Architecture Wizard will correctly tie the unused REL pin to GND.

AR# 23878
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article