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AR# 23884

v2.5 COREGen Aurora - Release Notes and Known Issues

Description

This Answer Record contains the v2.5 COREGen Aurora Release Notes and Known Issues.

Solution

New Features

- Updated for ISE 8.2i

- Added Virtex-4 FX CES4 calibration blocks, reset logic, and analog parameter settings

- Improved Simplex Partner test options

Bug Fixes - Virtex-4

- CR 206986: Refclk frequencies are incorrectly calculated for line rate values less than 2.5 Gb/s

- CR 225865: The Loopback Port is not connected in Aurora cores generated for Virtex-4

- CR 231348: Virtex-4 clock settings are incorrect for line rates at or below 1.25 Gb/s

Bug Fixes - Virtex-II Pro/Virtex-II Pro X

- CR 232670: Signal-extending registers inserted in the CHBONDI-CHBONDO path prevent Channel Bonding with Virtex-II Pro Aurora cores using both rows of MGTs from building correctly

- CR 232929: Clock Correction insert function on Aurora cores for Virtex-II Pro X, step 0, can cause data corruption

Bug Fixes - Generic

- CR 202853: Target device and HDL values should be determined by project settings.

- CR 203000: GUI permits generation of a five-lane module when placement is specified for only four lanes.

- CR 214838: SIMPLEX_PARTNER simulation script and testbench modules contain errors.

- CR 223628: COMBUS configuration is incompatible with Channel Bonding.

- CR 223630: Error_detect module incorrectly counts errors on soft error sequences.

- CR 224192: Rx_ll_ufc_datapath module is generated unnecessarily when no flow control is selected.

- CR 227400: On multi-lane Aurora cores, the TX system reset control monitors only one TXLOCK signal, potentially allowing portions of the design to run prior to receiving TXLOCK.

Known Issues

- None at time of release.

AR# 23884
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article