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This Answer Record for the CORE Generator contains the IP-DSP "What's New" and "Known Issues" addressed in 8.2i IP Update 2 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 23831).

New Features in v2.0:

- Support added for Virtex-5.

Bug Fixes in v2.0:

- CR 232447: Incorrect switching of alternate data couples.

Symptom: Incorrect data on PAR_Y2 and PAR_W2 outputs. The core was changed to comply with amendment Cor1/D5 of IEEE P802.16, which specifies switching of alternate data couples on ODD interleaver addresses.

- CR 234370: Corrected timing of RFFD output.

Symptom: If FD is sampled High on the first active clock edge after the core asserts RFFD, there are errors in PAR_Y2 and PAR_W2 outputs, and errors in the last bit of either or both systematic outputs. This occurs because the core asserts RFFD one clock too early.

The Direct Digital Synthesizer Compiler LogiCORE replaces the Direct Digital Synthesizer (DDS) core for all new designs.

New Features v1.0:

- First Release.

- Support for Virtex-II Pro,Virtex-4,Virtex-5, and Spartan-3.

Bug Fixes in v1.0:

- None.

The FIR Compiler LogiCORE replaces the LogiCORE Distributed Arithmetic FIR (DA FIR) Filter Core MAC FIR Filter Cores for all new designs.

New Features in v2.0:

- Support added for Virtex-5 and automotive variants of Virtex-4 and Spartan-3.

- Support added for ISE 8.2i.

- Exploits symmetry in most multi-rate filter implementations to reduce resource utilization.

- Quantization of real value coefficients, and plotting of ideal and quantized frequency response.

- Supports fixed P/Q resampling filter implementations.

- Supports wider ranges for channel and rate parameters.

- Enhanced support for Virtex-4 and Virtex-5 families:

-- Support for MAC-based Hilbert and Interpolated filter structures.

-- Core latency and resource estimation for DSP slices and block RAM now reported in the customization GUI.

Bug Fixes in v2.0:

- CR 223807: CORE Generator reports "Error:sim:57." This issue occurs when the ratio of clock frequency to sample frequency is significantly larger than the number of cycles required to perform the filter calculation, resulting in a synthesis error and failure to generate the core. See (Xilinx Answer 22675) for further information.

- CR 226141: ND signal does not operate as specified for single channel, fully parallel implementations, single rate half-band cases, or multi-channel decimating half-band filters. See (Xilinx Answer 23139), (Xilinx Answer 23088), or (Xilinx Answer 23091) for further information.

- CR 224243: Failure to generate single rate or interpolating half-band filter implementations when fully parallel architecture is used. See (Xilinx Answer 22705) for further information.

- CR 227184: Glitching might occur during switch-over between half-band coefficient sets, resulting in the center coefficient of the new half-band filter set being applied too early.

New Features in v3.0:

- Virtex-5 support, including:

-- New option allows adder to make use of DSP48E in Virtex-5 or DSP48 in Virtex-4.

-- Multiplier now supports DSP48E.

-- Option to construct single precision multiplier from 1 DSP48E + logic.

-- Low latency adder architecture supported on Virtex-5 implementations.

- Support for higher levels of pipelining in adder and multiplier for increased speed.

- Improved size and speed of square root.

- Conversion operations between floating-point types added.

- Resource and speed estimation provided in customization GUI.

- Support removed for Virtex and Spartan-II. Please use the v2.0 Core if targeting these architectures.

Bug Fixes in v3.0:

- CR 226251: Compare should have a result of 1-bit rather than use bit 0 of larger output.

New Features in v5.0:

- Support added for Virtex-5.

Bug Fixes in v5.0:

- None.

New Features in v6.0:

- Support added for Virtex-5 and Spartan-3A.

- Support removed for Virtex and Spartan-II. If targeting these architectures, please use the v5.1 Core.

- Support added for ISE 8.2i.

- Variable check symbol input added (R_IN).

- New control and monitoring signals added:

-- Marker bits (MARK_IN, MARK_OUT).

-- INFO_END output.

-- Bit Error Statistics outputs (BIT_ERR_0_TO_1, BIT_ERR_1_TO_0, BIT_ERR_RDY).

- Now uses XST to elaborate the design.

- UniSim simulation model for both VHDL and Verilog languages.

Bug Fixes in v6.0:

- None.

New Features in v3.0:

- Support added for Virtex-5.

- Trellis termination bits are now multiplexed by default onto three outputs over four cycles as specified by 3GPP TS 25.222 Para 4.2.3.2.2 (parallel output of trellis termination bits is still available as an option).

Bug Fixes in v3.0:

- None.

New Features in v3.0:

- Support added for Virtex-5.

- Support added for ISE 8.2i.

Bugs Fixed in v3.0:

- None.

New Features in v6.0:

- Support for ISE 8.2i added.

- Support added for Virtex-5 and Spartan-3A, including optimized area and speed architectures for the LUT6 fabric.

- Virtex-5 specific enhancements:

-- New speed option for the parallel configuration of the core (Virtex-5 only).

- General Enhancements:

-- Block RAM utilization reduced by 50% for parallel and multi-channel configurations.

-- Traceback length for standard traceback can now be any value between 12 and 128; previously, the length had to be divisible by 6. (Reduced latency traceback length still must be divisible by 6).

-- Core now uses Standard Traceback instead of Reduced Latency Traceback for multi-channel configurations.

-- The BER count output is no longer scaled by a factor of 8.

-- Internal puncturing support removed from the core. Erasure pins offer more flexible rate management.

-- New "Equal States" Trellis Initialization option allows all the states to be initialized to the same value.

-- New "Out of Synchronization" flag (oos_flag), for monitoring the synchronization status of the core.

-- Simplified GUI layout with tool tips.

-- UniSim simulation model support for both VHDL and Verilog languages.

Removed Support in v6.0

- Support removed for Virtex and Spartan-II. If targeting these architectures, please use v5.0 Core.

- Speed architecture option now only available on Virtex-5.

Bug Fixes in v6.0

- CR 217252: Sync remains High once it has been set, even in high noise environment. Synchronization now detects the case where there is no noise on the channel and asserts the out_of_sync pin appropriately.

- No Known Issues.

- Why are the outputs of my DDS Compiler always stuck at 6 and -6? See (Xilinx Answer 24179).

- Why can I not use the multi-column support when my coefficients are symmetrical? See (Xilinx Answer 22936).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

- <Distributed Arithmetic Filter Architecture:

-- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).

-- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).

-- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

- Multiply Accumulator Filter Architecture for all devices other than Virtex-4 and Virtex-5:

-- Why does my single rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"? See (Xilinx Answer 22706).

-- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).

-- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).

-- COE errors reported in wrong format. See (Xilinx Answer 14202).

-- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

- Why do I not see a resource estimation graph for my Floating Point operator function? See (Xilinx Answer 24039).

- No Known Issues.

- No Known Issues.

- No Known Issues.

- No Known Issues.

- No Known Issues.

- Why is my output result one less than the expected result? See (Xilinx Answer 23933).

- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).

- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).

- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).

- LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require four extra clocks after asserting the ND signal, before the data will be processed? See (Xilinx Answer 23934).

- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).

- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).

- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

- No Verilog model is available for the FFT Core. See (Xilinx Answer 11155).

- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

- Simulation of all fixed netlist FFT (64, 256, 1024) Cores generates many warnings. See (Xilinx Answer 14861).

- Information on output connections to the fixed netlist FFT (64, 256, 1024) Cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

- Large FFT point size generation times. See (Xilinx Answer 21988).

- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).

- When I set up my Multiply Accumulate v4.0 Core to have a wide input (e.g. 24x16) and use an output that is less than full precision, why is there no activity on the output of my core during simulation? See (Xilinx Answer 24096).

- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).

- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).

- COE Errors reported in wrong format. See (Xilinx Answer 14202).

- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

- Why does my Constant Coefficient Multiplier (CCM), with a constant of -1, fail to generate? See (Xilinx Answer 23700).

- Why is the optimum latency incorrect for symmetric hybrid-based multipliers, when targeting Virtex-II, Spartan-3, or Spartan-3E? See (Xilinx Answer 23703).

- Why is the output of my Constant Coefficient Multiplier (CCM) with a constant value of (2^64)-1 incorrect? See (Xilinx Answer 23704).

- Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining? See (Xilinx Answer 23705).

- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).

- Why can I not add handshaking signals to my multiplier? See (Xilinx Answer 23598).

- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).

- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).

- Why is the LogiCORE RAM-based Shift Register v9.0 almost 10 times larger than the LogiCORE RAM-based Shift Register v8.0, when targeting Virtex or Spartan-II?

See (Xilinx Answer 23696).

- How can I get the TPC to compile using XST, without incurring MAP Pack ERROR:Pack:679? See (Xilinx Answer 22258).

- Why does the reset need to be applied, in order for the code to be change? See (Xilinx Answer 24298).

- Why does the OutputRDY signal Remain high for 6 clock cycles after the output FIFO is empty? See (Xilinx Answer 24299).

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AR# 23902 | |
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Date Created | 09/04/2007 |

Last Updated | 03/30/2009 |

Status | Archive |

Type | General Article |