We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23914

MPMC2 - Is the MPMC2 available as VHDL?


MPMC2 IP Configurator versions: v1.6, v1.7, v1.8 and v1.9

The MPMC2 IP is supplied in Verilog source code. I want to simulate the MPMC2; is it also available in VHDL?


The MPMC2 is delivered as Verilog RTL only. There is no current plan to deliver VHDL RTL. If you have a VHDL-only simulator, you can generate a VHDL gate-level netlist for use in your simulation by following these steps in the Xilinx Platform Studio:

1. Open the Project Options dialog box by selecting Project --> Project Options.

2. Select the HDL and Simulation tab.

3. Select HDL - VHDL.

4. Unselect "Allow Mixed Language Behavioral Files."

When you generate the simulation files, the MPMC2 is a gate-level (post-synthesis) VHDL netlist. The generation of the simulation files is performed by Simulation --> Generate Simulation HDL Files.
AR# 23914
Date Created 09/04/2007
Last Updated 11/12/2010
Status Archive
Type General Article