UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23948

9.1i EDK - Temac testapp_peripheral example does not work because of the ML405/ML410 PHY Address Setting

Description

Keywords: ML405, ML410, PHY, address, settings

ML405 PHY address and the MDIO bus

The PHY layer interface to the network is provided by an external PHY chip on the ML series of development boards. Some of the ML series of boards provide multiple network connections by using a unique PHY device per network connection.

A PHY contains interfaces for data, clock, control, and device management. On power-up the PHY device auto-negotiates with its link partner on a set of common operating conditions (e.g., speed, duplex, etc.). The PHY register settings can subsequently be modified through software control.

The IEEE 802.3 workgroup specified the Management Data Input/Output (MDIO) two-pin standard to define how controllers can access and modify the various registers within a PHY device. Since a PHY device can share the MDIO interface with up to 30 other PHY devices, each PHY device requires a unique address.

All production ML405 boards are strapped to PHY address 0x07. A limited number of pre-production boards, identifiable with serial numbers less than S/N 0606001 or only 6-digits long, are strapped to PHY address 0x00. The S/N label can be found on the PCB near the CompactFlash connector. The CompactFlash card must be removed to view the S/N label.


Why did the PHY address change?

A PHY address of 0x00 is reserved as the broadcast address. This does not pose a problem unless there are multiple PHY devices attached to a common MDIO bus. The ML405 supports multiple user selectable methods of connecting the FPGA to the external Ethernet PHY. One of these connection methods (SGMII) places an internal PHY onto the MDIO bus connected to the external PHY device. To provide unambiguous PHY access in this multiple PHY scenario, the address of the external PHY is set to 0x07 on all production boards.


Verifying Network Functionality

The standalone software application, Ping Responder, replies to any ping requests it receives. This code is posted in the RGMII and SGMII sections, of the pre-production ML410 page:
http://www.xilinx.com/ml410-p
and can be ported to the ML405.

All Rev D and greater ML410 boards have their PHY address strapped to 0x07 (and provide MGTs/SGMII support). A limited number of pre-production ML410 boards (all Rev C and earlier) have their PHY address strapped to 0x00 (and do not provide MGTs/SGMII, but offer MII and RGMII support).

The Ping Responder application contains code (mdio.c) that detects if it is running on a board with PHY address 0x00 or 0x07. This code can be used to scan for any manufacturer's PHY, since all PHYs contain a unique manufacturer's ID in Register 2, the PHY identifier register.

Solution

ML405 8.2i TestApp_Peripheral

Starting with EDK 8.2i SP1, Base System Builder (BSB) can be used to generate an ML405 design that contains a hard_temac peripheral. The BSB generated TestApp_Peripheral code used to perform a quick TEMAC loopback test needs to be changed to use the production ML405 PHY address.

In the file "xtemac_example.h", perform the following edit:

Change from:
#define TEMAC_PHY_ID 0

to:
#define TEMAC_PHY_ID 7

AR# 23948
Date Created 09/06/2006
Last Updated 08/20/2007
Status Active
Type General Article