LogiCORE RapidIO v3.1 Rev 2 - Simulation Only Evaluation License generates incomplete simulation file and cannot simulate on PC
Description
Keywords: CORE Generator, COREGen, ip1_i, IP Update 1, serial, parallel, high, speed, high-speed, PHY, logical, design environment, RIO, SRIO
When I generate a Serial RapidIO PHY layer Core v3.1 with the evaluation license (simulation-only license, provided with the IP Update #1), the generated simulation file is incomplete. The file size is approximately 62 Kbytes when it should be over 8 Mbytes. This issue is observed on the PC Windows, but not on Linux machines.
Also, even if the file gets generated, the simulation will not work; simulation continues to run forever.
Solution
Generate Serial RapidIO Core on the Linux system and run simulation on Windows.Once the files are generated, you will need to modify the MTI simulator script file: simulate_mti.do
1. vlog \$XILINX/verilog/src/glbl.v
change this line to:
vlog $env(XILINX)/verilog/src/glbl.v
($XILINX is not recognized on Windows MTI)
2. run -all
change this line to:
run 70 us
(run -all will cause the simulation to run forever)
3. add
$finish
at the end of the script.
(You must specify $finish for the wave window to open.)
This problem has been addressed in the Serial RapidIO v4.1 Core.